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    Storage device and latch management method thereof
    1.
    发明授权
    Storage device and latch management method thereof 有权
    存储设备及其锁存管理方法

    公开(公告)号：US09384803B2

    公开(公告)日：2016-07-05

    申请号：US14468936

    申请日：2014-08-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Soo Park ,  Moosung Kim ,  Taekyun Kang

    IPC: G11C7/20 ,  G11C5/14 ,  G11C16/30

    CPC classification number: G11C7/20 ,  G11C5/148 ,  G11C16/30 ,  G11C2207/2227

    Abstract: A latch management method of a storage device includes permitting the storage device to enter a reduced power mode in which the storage device operates with a reduced power. The method includes reading initial latch data stored in the at least one nonvolatile memory device in response to the entering operation. The method includes setting latches associated with the at least one nonvolatile memory device based on the read initial latch data.

    Abstract translation: 存储装置的锁存管理方法包括允许存储装置进入存储装置以降低的功率运行的降低功率模式。 该方法包括响应于输入操作读取存储在至少一个非易失性存储器件中的初始锁存数据。 该方法包括基于读取的初始锁存数据来设置与至少一个非易失性存储器件相关联的锁存器。

    Page buffer circuit and memory device including the same
    2.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US12277995B2

    公开(公告)日：2025-04-15

    申请号：US17988797

    申请日：2022-11-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin-Young Chun ,  Minjae Seo ,  Moosung Kim

    IPC: G11C7/10 ,  G11C7/12 ,  G11C7/20

    Abstract: A non-volatile memory device includes: a memory cell; a bit line connected to the memory cell; a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line; a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter; and a control circuit for operating the first transistor and the second transistor at least once for at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged.

    Memory controller and memory system including the same
    3.
    发明授权
    Memory controller and memory system including the same 有权

    公开(公告)号：US10169227B2

    公开(公告)日：2019-01-01

    申请号：US15704888

    申请日：2017-09-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moosung Kim ,  Dawoon Jung

    IPC: G06F12/02 ,  G11C16/26 ,  G11C11/56

    Abstract: An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request.

    METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION
    4.
    发明申请
    METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION 审中-公开
    操作有效的错误检测的非易失性存储器件的操作方法

    公开(公告)号：US20150248930A1

    公开(公告)日：2015-09-03

    申请号：US14712939

    申请日：2015-05-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

    IPC: G11C11/56 ,  G11C16/34

    CPC classification number: G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

    Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

    Abstract translation: 操作非易失性存储器件的方法可以包括识别非易失性存储器件中的一个或多个多位非易失性存储器单元，其经历从擦除状态到至少部分编程状态的无意编程。 可以通过执行多个读取操作来生成错误检测数据，然后解码错误检测数据以识别具有错误的特定单元，来检测在编程第一多个多位非易失性存储器单元的操作期间产生的错误。 可以读取编程的第一多个多位非易失性存储单元和在编程操作期间被修改的强位数据向量，以支持错误检测。 然后可以将该数据连同从与第一多个多位非易失性存储器单元相关联的页面缓冲器读取的数据解码以识别第一多个多位非易失性存储器单元中的哪一个是无意编程的单元。

    Nonvolatile memory device performing read operation with variable read voltage
    8.
    发明授权
    Nonvolatile memory device performing read operation with variable read voltage 有权
    非易失性存储器件以可变的读取电压进行读取操作

    公开(公告)号：US09007839B2

    公开(公告)日：2015-04-14

    申请号：US13915688

    申请日：2013-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Sang Lee ,  Moosung Kim

    IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3454 ,  G11C16/3495 ,  G11C2211/5641

    Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

    Abstract translation: 读取非易失性存储器件的方法包括将读取电压施加到存储器单元阵列以读取所选择的存储器单元，对具有高于或低于读取电压的阈值电压的所选存储单元的数量进行计数，以及将所计数的数目 具有用于确定存储在所选择的存储器单元中的位数的参考值。

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