公开(公告)号：US20220139956A1

公开(公告)日：2022-05-05

申请号：US17578965

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sunggil KIM ,  Seulye KIM ,  HongSuk KIM ,  Phil Ouk NAM ,  Jaeyoung AHN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/11524 ,  H01L27/11556

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20200266213A1

公开(公告)日：2020-08-20

申请号：US16870082

申请日：2020-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20240018657A1

公开(公告)日：2024-01-18

申请号：US18373364

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hyun YANG ,  Sang Yub IE ,  Tae Yong KIM ,  Phil Ouk NAM

IPC: C23C16/455 ,  H01L21/67 ,  H01L21/673

CPC classification number: C23C16/45578 ,  C23C16/45595 ,  C23C16/45546 ,  H01L21/67 ,  H01L21/673

Abstract: A semiconductor manufacturing apparatus including a process chamber and a boat having a support member supporting substrates arranged in a first direction. An inner tube encloses the boat and includes a slit along a side wall. A nozzle supplies a process gas and includes a gas injection port at a position corresponding to the slit. The gas injection port includes a first inlet and first outlet. The slit includes a second inlet and second outlet. A distance to an end of the first inlet from a center line that connects a center of the first inlet and a center of the second outlet is different from the distance from the center line to an end of the first outlet and/or a distance from the center line to an end of the second inlet is different from a distance from the center line to an end of the second outlet.

公开(公告)号：US20200243554A1

公开(公告)日：2020-07-30

申请号：US16845236

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sup LEE ,  Phil Ouk NAM ,  Sung Yun LEE ,  Chang Seok KANG

IPC: H01L27/11575 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11578

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

公开(公告)号：US20220068968A1

公开(公告)日：2022-03-03

申请号：US17523014

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20200243558A1

公开(公告)日：2020-07-30

申请号：US16845615

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sunggil KIM ,  Seulye KIM ,  HongSuk KIM ,  Phil Ouk NAM ,  Jaeyoung AHN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20180261618A1

公开(公告)日：2018-09-13

申请号：US15722485

申请日：2017-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sup LEE ,  Phil Ouk NAM ,  Sung Yun LEE ,  Chang Seok KANG

IPC: H01L27/11575 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11575 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

公开(公告)号：US20240251553A1

公开(公告)日：2024-07-25

申请号：US18493122

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Bong SHIN ,  Ji Hoon LEE ,  Mi Hye KANG ,  Jun Hee NA ,  Phil Ouk NAM ,  Tae Gi YEH

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes a stack structure on a substrate, extending in a first direction, and including gate electrode layers and insulating layers stacked alternately with each other, a vertical structure including a vertical channel film extending in a second direction crossing the first direction and a channel insulating film disposed on the vertical channel film and having first areas adjacent to the insulating layers and second areas adjacent to the gate electrode layers, and a high-k film on the channel insulating film. The high-k film includes a first high-k metal oxide film between the first areas and the insulating layers and in contact with the first areas and a second high-k metal oxide film between the second areas and the gate electrode layers and in contact with the second areas, and the first and second high-k metal oxide films include different metal materials.

公开(公告)号：US20220223616A1

公开(公告)日：2022-07-14

申请号：US17711826

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sup LEE ,  Phil Ouk NAM ,  Sung Yun LEE ,  Chang Seok KANG

IPC: H01L27/11575 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11578

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

公开(公告)号：US20210108313A1

公开(公告)日：2021-04-15

申请号：US16983142

申请日：2020-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hyun YANG ,  Sang Yub IE ,  Tae Yong KIM ,  Phil Ouk NAM

IPC: C23C16/455

Abstract: A semiconductor manufacturing apparatus including a process chamber and a boat having a support member supporting substrates arranged in a first direction. An inner tube encloses the boat and includes a slit along a side wall. A nozzle supplies a process gas and includes a gas injection port at a position corresponding to the slit. The gas injection port includes a first inlet and first outlet. The slit includes a second inlet and second outlet. A distance to an end of the first inlet from a center line that connects a center of the first inlet and a center of the second outlet is different from the distance from the center line to an end of the first outlet and/or a distance from the center line to an end of the second inlet is different from a distance from the center line to an end of the second outlet.