公开(公告)号：US11961793B2

公开(公告)日：2024-04-16

申请号：US17562157

申请日：2021-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uk Kim

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L23/49827 ,  H01L25/0652 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2924/013

Abstract: A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.

公开(公告)号：US09620484B2

公开(公告)日：2017-04-11

申请号：US15051171

申请日：2016-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Kim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L23/538 ,  H01L23/28 ,  H01L25/10 ,  H01L23/13 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/10 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package.

公开(公告)号：US12080619B2

公开(公告)日：2024-09-03

申请号：US17723347

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uk Kim ,  Ki Wook Jung

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/538 ,  H01L25/18 ,  H01L49/02

CPC classification number: H01L23/373 ,  H01L23/367 ,  H01L23/5385 ,  H01L25/18 ,  H01L28/40

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a capacitor disposed on the substrate and spaced apart from the first semiconductor chip in a first direction; an insulating layer disposed on the substrate and covering the capacitor; a first heat conductive layer at least partially surrounding side walls of the first semiconductor chip and disposed on the insulating layer, wherein the first heat conductive layer is in contact with the side walls of the first semiconductor chip, and wherein the first heat conductive layer includes a first material that is a conductive material; and a second heat conductive layer disposed on the first heat conductive layer, wherein the second heat conductive layer is in contact with the first heat conductive layer, wherein the second heat conductive layer includes a second material that is a non-conductive material.

公开(公告)号：US11978695B2

公开(公告)日：2024-05-07

申请号：US17513282

申请日：2021-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/49822 ,  H01L21/4807 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/49866 ,  H01L23/642 ,  H01L24/08 ,  H01L24/48 ,  H01L28/40 ,  H01L2224/08235 ,  H01L2224/48227

Abstract: A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having a first opening and a second opening that penetrate the connection substrate, a semiconductor chip on the first redistribution substrate and in the first opening of the connection substrate, a chip module on the first redistribution substrate and in the second opening of the connection substrate, and a molding layer that covers the semiconductor chip, the chip module, and the connection substrate. The chip module includes an inner substrate and a first passive device on the inner substrate. In the second opening, the molding layer covers the first passive device on the inner substrate.

公开(公告)号：US11101253B2

公开(公告)日：2021-08-24

申请号：US17036053

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uk Kim

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/498

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip.

公开(公告)号：US10510672B2

公开(公告)日：2019-12-17

申请号：US15956414

申请日：2018-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Kim ,  Sunchul Kim ,  Jinkyeong Seol ,  Byoung Wook Jang

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.