公开(公告)号：US20250062248A1

公开(公告)日：2025-02-20

申请号：US18934816

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20240379478A1

公开(公告)日：2024-11-14

申请号：US18780720

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun SHIN ,  Junyeong HEO

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20250167137A1

公开(公告)日：2025-05-22

申请号：US19027551

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20240178191A1

公开(公告)日：2024-05-30

申请号：US18467330

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihun JUNG ,  Unbyoung KANG ,  Yeongkwon KO ,  Seunghun SHIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08146

Abstract: A semiconductor chip including a semiconductor substrate having an active surface and a non-active surface opposite to each other, a plurality of through electrodes passing through the semiconductor substrate, a plurality of wiring structures on the active surface and electrically connected to the plurality of through electrodes, an inter-wire insulating layer surrounding the plurality of wiring structures, a plurality of front chip connection pads electrically connected to the plurality of wiring structures, a front insulating layer surrounding the plurality of front chip connection pads, on the inter-wire insulating layer, a plurality of rear chip connection pads disposed on the non-active surface and electrically connected to the plurality of through electrodes, and a rear insulating layer surrounding the plurality of rear chip connection pads, on the non-active surface, wherein the front insulating layer includes a cover insulating portion covering a side surface of the inter-wire insulating layer may be provided.

公开(公告)号：US20220013474A1

公开(公告)日：2022-01-13

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Yeongkwon KO ,  Jayeon LEE ,  Jaeeun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US20250167031A1

公开(公告)日：2025-05-22

申请号：US18890154

申请日：2024-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hosin SONG ,  Yeongkwon KO ,  Jiyoung PARK ,  Junyeong HEO

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/66 ,  H01L21/68

Abstract: A carrier substrate according to some example embodiments is a carrier substrate having a circular disk shape, and includes a first surface, a second surface opposite surface to first surface, and an inclined surface that extends along the edge of the first surface, has an inclination angle from the first surface, and is configured to reflect incident light from the second surface.

公开(公告)号：US20240297150A1

公开(公告)日：2024-09-05

申请号：US18500311

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongpa HONG ,  Yeongkwon KO ,  Gunho CHANG ,  Wonkeun KIM ,  Wonyoung KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, the first semiconductor chip including first through-vias, first bump structures on the first front surface of the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips including second through-vias, adhesive layers respectively on the second front surfaces of the plurality of second semiconductor chips, and an encapsulant between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips. The adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip.

公开(公告)号：US20240162194A1

公开(公告)日：2024-05-16

申请号：US18421198

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20210343613A1

公开(公告)日：2021-11-04

申请号：US17117588

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun SHIN ,  Junyeong HEO

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20230178499A1

公开(公告)日：2023-06-08

申请号：US18162878

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/13

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0652 ,  H01L23/13 ,  H01L2924/3512 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.