-
公开(公告)号：US12154616B2
公开(公告)日：2024-11-26
申请号：US18493051
申请日：2023-10-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yoon-Joo Eom , Seungjun Bae , Hye Jung Kwon , Young-Ju Kim
IPC: G11C7/14 , G11C5/14 , G11C7/02 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C11/4093 , G11C11/4096 , G11C29/02 , G11C29/50
Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
-
公开(公告)号：US11862234B2
公开(公告)日：2024-01-02
申请号：US17457077
申请日：2021-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yoon-Joo Eom , Seungjun Bae , Hye Jung Kwon , Young-Ju Kim
IPC: G11C7/20 , G11C11/4093 , G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C11/4096 , G11C7/14 , G11C7/02 , G11C29/50 , G11C11/4072 , G11C29/02 , G11C7/10 , G11C5/14
CPC classification number: G11C11/4093 , G11C5/147 , G11C7/02 , G11C7/1069 , G11C7/14 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C11/4087 , G11C11/4091 , G11C11/4096 , G11C29/028 , G11C29/50 , G11C29/021 , G11C29/023 , G11C2207/2254
Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
-
公开(公告)号：US11195571B2
公开(公告)日：2021-12-07
申请号：US16136895
申请日：2018-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yoon-Joo Eom , Seungjun Bae , Hye Jung Kwon , Young-Ju Kim
IPC: G11C11/4093 , G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C11/4096 , G11C7/14 , G11C7/20 , G11C7/02 , G11C29/50 , G11C11/4072 , G11C29/02 , G11C7/10 , G11C5/14
Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
-
公开(公告)号：US10734043B2
公开(公告)日：2020-08-04
申请号：US16054633
申请日：2018-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Ju Kim , Dong-Seok Kang , Hye Jung Kwon , Byungchul Kim , Seungjun Bae
IPC: G11C8/00 , G11C7/10 , H03L7/08 , G11C8/18 , G11C11/408 , G11C11/4096 , G11C11/4076 , G11C29/02 , G11C7/22 , G11C7/02 , G06F13/42 , G11C11/4093 , G06F13/16
Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.
-
公开(公告)号：US10666467B2
公开(公告)日：2020-05-26
申请号：US16108894
申请日：2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye Jung Kwon , Seungjun Bae , Yongjae Lee , Young-Sik Kim , Young-Ju Kim , Suyeon Doo , Yoon-Joo Eom
Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
-
Patent Agency Ranking
公开(公告)号：US10693969B2
公开(公告)日：2020-06-23
申请号：US16230918
申请日：2018-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ki-Soo Cho , Aravind Iyer , Mahesh Anjanappa , Ranjeet Kumar Patro , Prasad Tirumala Sree Hari Vara Vadlapudi , Suck-Ho Seo , In-Hyuk Choi , Il-Sung Hong , Abhijit C Pathak , Amit Prabhudesai , Ashok Subash , Ravindra Balkrishna Shet , Dong-Hyoun Son , Byeong-Ho Shim , Ji-Ryang Chung , Kangli Hao , Madhavan Vasudevan , Mahesh Malagouda Patil , M. S. S. K. Sharma , Ranjitsinh Udaysinh Wable , Shekhar Anantha Ambekar , Subba Reddy Venkata Kota , Raghavendra Vaddarahalli Ramegowda , Varunjith Therath Kainoth , Vishwanath Balekudige Gopalakrishna , Nam-Kun Kim , Young-Ju Kim , Jeong-Mi Kim , Chang-Sik Kim , Hyeong-Geun Kim , Shashanka Dasari , Gyu-Seok Shim , Won-Geun Shim , Anil Agiwal , Jin-Hyuk Lee , Sang-Hyun Han , In-Hyup Hwang , Ji-Young Hwang
Abstract: An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs.
-
公开(公告)号：US10649849B2
公开(公告)日：2020-05-12
申请号：US15938092
申请日：2018-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Hun Kim , Su-Yeon Doo , Dong-Seok Kang , Hye-Jung Kwon , Young-Ju Kim
Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.
-
公开(公告)号：US11133571B2
公开(公告)日：2021-09-28
申请号：US15766249
申请日：2016-10-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Chul Park , Yeon-Woo Kim , Jong-Hyuk Kim , Seung-Gil Jeon , Young-Ju Kim , Chae-Man Lim
IPC: H01Q1/24 , H01Q21/00 , H04W88/06 , H01Q5/50 , H04B7/06 , H04B7/08 , H01Q3/24 , H01Q9/42 , H01Q1/44 , H04B1/00
Abstract: An electronic apparatus, according to various embodiments of the present invention, comprises: a first antenna of a first bandwidth; a second antenna of a second bandwidth which partially overlaps with the first bandwidth; a third antenna of the first bandwidth; a fourth antenna of the second bandwidth; a transmission/reception path corresponding to each of a plurality of bandwidths; a reception path corresponding to each of the plurality of bandwidths; and a path formation unit which forms a path such that any one of the first antenna and the third antenna is connected to the transmission/reception path, the other of the first antenna and the third antenna is connected to the reception path, and any one of the second antenna and the fourth antenna is connected to the transmission/reception path, and the other of the second antenna and the fourth antenna is connected to the reception path.
-
公开(公告)号：US20190158320A1
公开(公告)日：2019-05-23
申请号：US16108894
申请日：2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye Jung Kwon , Seungjun Bae , Yongjae Lee , Young-Sik Kim , Young-Ju Kim , Suyeon Doo , Yoon-Joo Eom
Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
-
公开(公告)号：US10262935B2
公开(公告)日：2019-04-16
申请号：US15677054
申请日：2017-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-Ju Kim , Su-A Kim , Soo-Young Kim , Min-Woo Won , Bok-Yeon Won , Ji-Suk Kwon , Young-Ho Kim , Ji-Hak Yu , Hyun-Chul Yoon , Seok-Jae Lee , Sang-Keun Han , Woong-Dai Kang , Hyuk-Joon Kwon , Bum-Jae Lee
IPC: H01L23/522 , G11C11/408 , G11C11/4091 , G11C11/4097 , H01L23/528 , H01L23/00 , H01L23/50 , H01L23/552 , G11C7/10 , G11C7/06
Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.017 seconds)
