公开(公告)号：US20220319620A1

公开(公告)日：2022-10-06

申请号：US17841411

申请日：2022-06-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Steven LEMKE ,  Nha NGUYEN ,  Vipin TIWARI ,  Nhan DO

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/063 ,  G06F3/06 ,  G06N3/08 ,  G11C16/26 ,  G11C29/10

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

公开(公告)号：US20240095511A1

公开(公告)日：2024-03-21

申请号：US18522153

申请日：2023-11-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN ,  Nhan DO

IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

CPC classification number: G06N3/065 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

公开(公告)号：US20230229887A1

公开(公告)日：2023-07-20

申请号：US18123918

申请日：2023-03-20

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh BAYAT ,  Xinjie GUO ,  Dmitri STRUKOV ,  Nhan DO ,  Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

公开(公告)号：US20220398444A1

公开(公告)日：2022-12-15

申请号：US17893071

申请日：2022-08-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Steven LEMKE ,  Nha NGUYEN ,  Vipin TIWARI ,  Nhan DO

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer; verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value; repeating the programming and verifying for each of the N values; and identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.

公开(公告)号：US20140293724A1

公开(公告)日：2014-10-02

申请号：US14229763

申请日：2014-03-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Samar SAHA

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C16/28 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/792

Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

Abstract translation: 公开了用于通过使用具有差分阈值电压的MOS晶体管来提供选择性阈值电压特性的系统和方法。 在一个示例性实施例中，提供了一种金属氧化物半导体器件，其包括半导体材料的衬底，其具有源极区，漏极区和它们之间的沟道区，沟道区上方的绝缘层和绝缘层的栅极部。 此外，关于器件，绝缘层的形状和/或接合区域的形状或注入在栅极 - 漏极和栅极 - 源极结之间具有不同的尺寸，以提供不同的阈值电压 他们。

公开(公告)号：US20140269098A1

公开(公告)日：2014-09-18

申请号：US13830207

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Anh LY ,  Thuan VU ,  Hung Quoc NGUYEN

IPC: G11C16/12

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Abstract translation: 公开了用于编程高级纳米闪存单元的改进的方法和装置。

公开(公告)号：US20240112729A1

公开(公告)日：2024-04-04

申请号：US18076129

申请日：2022-12-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Stephen TRINH ,  Stanley HONG ,  Thuan VU ,  Anh LY ,  Fan LUO

IPC: G11C11/56 ,  G06N3/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G06N3/04 ,  G11C11/5671 ,  G11C16/10 ,  G11C2216/04

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

公开(公告)号：US20240105263A1

公开(公告)日：2024-03-28

申请号：US18536123

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stanley HONG ,  Stephen TRINH ,  Anh LY ,  Nhan DO ,  Mark REITEN

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

公开(公告)号：US20200151543A1

公开(公告)日：2020-05-14

申请号：US16746852

申请日：2020-01-18

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh BAYAT ,  Xinjie GUO ,  Dmitri STRUKOV ,  Nhan DO ,  Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN

IPC: G06N3/04 ,  G06F3/06 ,  G06N3/063

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

公开(公告)号：US20140282348A1

公开(公告)日：2014-09-18

申请号：US13830267

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hung Quoc NGUYEN ,  Hieu Van TRAN ,  Hung Thanh NGUYEN ,  Anh LY ,  Thuan VU

IPC: G06F17/50

CPC classification number: G11C16/08 ,  G06F17/5081 ,  G11C7/062 ,  G11C8/10 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26 ,  G11C16/28

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于高级纳米闪存器件中的感测电路的改进的PMOS和NMOS晶体管设计。