公开(公告)号：US10199109B2

公开(公告)日：2019-02-05

申请号：US15371496

申请日：2016-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Kai Man Yue ,  Qing Rao ,  Lisa Bian

IPC: G11C16/28 ,  G11C16/26 ,  G11C16/24 ,  G11C7/06 ,  G11C7/14 ,  G11C16/04 ,  G11C16/32

Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.

公开(公告)号：US09601500B2

公开(公告)日：2017-03-21

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US20160379941A1

公开(公告)日：2016-12-29

申请号：US15258069

申请日：2016-09-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L23/00 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US10586595B2

公开(公告)日：2020-03-10

申请号：US16118272

申请日：2018-08-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Kai Man Yue ,  Guang Yan Luo

IPC: G11C16/04 ,  G11C16/26

Abstract: A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system comprises an array of flash memory cells organized into rows and columns, where each row is coupled to a word line and a control gate line.

公开(公告)号：US20170194055A1

公开(公告)日：2017-07-06

申请号：US15371496

申请日：2016-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Kai Man Yue ,  Qing Rao ,  Lisa Bian

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/2254

Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.

公开(公告)号：US09633735B2

公开(公告)日：2017-04-25

申请号：US14486687

申请日：2014-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Nhan Do ,  Yuri Tkachev ,  Kai Man Yue ,  Xiaozhou Qian ,  Ning Bai

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/12 ,  G11C29/02

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/12 ,  G11C16/16 ,  G11C29/021 ,  G11C29/028

Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

公开(公告)号：US20150078081A1

公开(公告)日：2015-03-19

申请号：US14386814

申请日：2013-03-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Yao Zhou ,  Xiaozhou Qian ,  Kai Man Yue ,  Guangming Lin

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C16/28 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028

Abstract: A trimmable current reference generator for use in a sense amplifier is disclosed

Abstract translation: 公开了一种用于读出放大器的可调整电流参考发生器

公开(公告)号：US10546646B2

公开(公告)日：2020-01-28

申请号：US16117987

申请日：2018-08-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qiang ,  Xiao Yan Pi ,  Kai Man Yue ,  Li Fang Bian

IPC: G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C16/24

Abstract: An improved low-power sense amplifier for use in a flash memory system is disclosed. The reference bit line and selected bit line are pre-charged during a limited period and with limited power consumed. The pre-charge circuit can be trimmed during a configuration process to further optimize power consumption during the pre-charge operation.

公开(公告)号：US09997252B2

公开(公告)日：2018-06-12

申请号：US15706586

申请日：2017-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiao Yan Pi ,  Xiaozhou Qian ,  Kai Man Yue ,  Yao Zhou ,  Yaohua Zhu

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/08 ,  G11C7/14 ,  G11C16/24 ,  G11C7/06 ,  G11C29/02 ,  G11C7/12 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

公开(公告)号：US20160254269A1

公开(公告)日：2016-09-01

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract translation: 一种存储器件，其包括多个ROM单元，每个ROM单元具有形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，设置在沟道区域的第一部分上方并与沟道区域的第一部分绝缘的第一栅极， 与沟道区的第二部分绝缘，以及在多个ROM单元上延伸的导电线。 导电线电耦合到ROM单元的第一子组的漏极区域，并且不电耦合到ROM单元的第二子组的漏极区域。 或者，ROM单元的第一子组各自包括沟道区域中的较高电压阈值注入区域，而ROM单元的第二子组每个在沟道区域中都缺少任何较高电压阈值注入区域。