公开(公告)号：US09356008B2

公开(公告)日：2016-05-31

申请号：US14616013

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Hsin-Ta Lin ,  Fu-Tang Huang ,  Yu-Po Wang ,  Lung-Yuan Wang ,  Chu-Chi Hsu ,  Chia-Kai Shih

IPC: H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31

CPC classification number: H01L25/162 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05078 ,  H01L2224/0519 ,  H01L2224/05561 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/06132 ,  H01L2224/06181 ,  H01L2224/11825 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13671 ,  H01L2224/1369 ,  H01L2224/1401 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0635 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Abstract translation: 提供一种半导体封装，其包括：第一半导体器件，其具有第一顶表面和与第一顶表面相对的第一底表面; 形成在所述第一半导体器件的所述第一顶表面上的多个导电球; 具有第二顶表面和与第二顶表面相对的第二底表面的第二半导体器件; 以及形成在所述第二半导体器件的所述第二底表面上并相应地接合到所述导电球以用于电连接所述第一半导体器件和所述第二半导体器件的多个导电柱，其中所述导电柱的高度小于300μm。 因此，本发明可以容易地控制半导体封装的高度，并且可应用于具有细间距导电球的半导体封装。

公开(公告)号：US10199345B2

公开(公告)日：2019-02-05

申请号：US15867008

申请日：2018-01-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

公开(公告)号：US09899344B2

公开(公告)日：2018-02-20

申请号：US14981549

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/2064

Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

公开(公告)号：US20180138140A1

公开(公告)日：2018-05-17

申请号：US15867008

申请日：2018-01-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/2064

Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

公开(公告)号：US20160358873A1

公开(公告)日：2016-12-08

申请号：US14981549

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/2064

Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

Abstract translation: 提供了一种衬底结构，其包括：具有多个导电焊盘的衬底本体; 绝缘层，形成在所述基板主体上并暴露所述导电焊盘; 形成在所述绝缘层中并电连接到所述导电焊盘的多个导电通孔; 形成在导电通孔和绝缘层中的多个电路，其中电路的宽度大于导电通孔的宽度; 以及形成在电路和绝缘层上的多个导电柱，其中每个导电柱具有大于或等于每个电路的宽度的宽度。 导电通孔，电路和导电柱一体形成。 因此，微芯片或细间距导电焊盘可以倒装芯片方式电连接到衬底结构。