公开(公告)号：US20160079110A1

公开(公告)日：2016-03-17

申请号：US14849639

申请日：2015-09-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuan-Wei Chuang ,  Shih-Kuang Chiu ,  Chun-Tang Lin ,  Jung-Pang Huang

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L21/6835 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/18162

Abstract: A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.

Abstract translation: 提供一种半导体封装，其包括：载体; 具有多个开口的框架，其中所述框架结合到所述载体并且由与所述载体的材料不同的材料制成; 分别设置在框架的开口中的多个电子元件; 形成在框架的开口中的密封剂，用于封装电子元件; 以及形成在电子元件上并电连接到电子元件的电路层。 通过精确地控制框架的开口的尺寸，本发明提高了电子元件的定位精度，从而提高后续处理中的产品产量。

公开(公告)号：US20140134797A1

公开(公告)日：2014-05-15

申请号：US14013512

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Yuan Chi ,  Jung-Pang Huang ,  Yan-Heng Chen ,  Hsi-Chang Hsu ,  Chiang-Cheng Chang ,  Shih-Kuang Chiu

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.

Abstract translation: 公开了一种制造半导体封装件的方法，其包括以下步骤：提供具有释放层和依次在其上形成的粘合剂层的载体; 在所述粘合剂层上设置多个半导体芯片; 在粘合剂层上形成密封剂以封装半导体芯片; 将衬底设置在密封剂上; 将释放层暴露于通过载体的光，以便去除释放层和载体; 然后去除粘合剂层，从而有效地防止半导体芯片暴露于光，以避免对半导体芯片的任何光损坏。

公开(公告)号：US20140117537A1

公开(公告)日：2014-05-01

申请号：US13729759

申请日：2012-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chen-Han Lin ,  Kuo-Hsiang Li ,  Jung-Pang Huang ,  Nan-Jia Huang ,  Hsin-Yi Liao

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package including an encapsulant having a top surface and a bottom surface opposite to the top surface; a semiconductor chip embedded in the encapsulant having an active surface, an inactive surface opposite to the active surface, and lateral surfaces interconnecting the active surface and the inactive surface, wherein the active surface protrudes from the bottom surface of the encapsulant and the semiconductor chip further has a plurality of electrode pads disposed on the active surface; a positioning member layer formed on a portion of the bottom surface of the encapsulant, covering the lateral surfaces of the semiconductor chip that protrude therefrom, and exposing the active surface; and a build-up trace structure disposed on the active surface of the semiconductor chip and the positioning member layer formed on the bottom surface of the encapsulant. The present invention also provides a method of fabricating a semiconductor package.

Abstract translation: 公开了一种半导体封装，其包括具有顶表面和与顶表面相对的底表面的密封剂; 嵌入密封剂中的半导体芯片具有活性表面，与活性表面相对的非活性表面以及将活性表面和非活性表面互连的侧表面，其中活性表面从密封剂的底表面和半导体芯片进一步突出 具有设置在有源表面上的多个电极焊盘; 定位构件层，形成在所述密封剂的底面的一部分上，覆盖从其突出的半导体芯片的侧表面，并露出所述活性表面; 以及设置在半导体芯片的有源表面上的积聚迹线结构和形成在密封剂的底表面上的定位构件层。 本发明还提供一种制造半导体封装的方法。

公开(公告)号：US09812340B2

公开(公告)日：2017-11-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

公开(公告)号：US09324585B2

公开(公告)日：2016-04-26

申请号：US13654754

申请日：2012-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US08895367B2

公开(公告)日：2014-11-25

申请号：US13964465

申请日：2013-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/36 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。

公开(公告)号：US20140183721A1

公开(公告)日：2014-07-03

申请号：US13846579

申请日：2013-03-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yan-Heng Chen ,  Chiang-Cheng Chang ,  Jung-Pang Huang ,  Hsi-Chang Hsu ,  Yan-Yi Liao

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.

Abstract translation: 提供一种半导体封装的制造方法，其包括以下步骤：提供具有粘合层和至少具有保护层的半导体元件的载体; 通过保护层将半导体元件设置在载体的粘合剂层上; 在用于封装半导体元件的载体的粘合剂层上形成密封剂; 去除载体和粘合剂层以将保护层暴露于密封剂; 以及去除所述保护层以使所述半导体元件暴露于所述密封剂。 由于半导体元件被保护层保护以防止在去除粘合剂层的过程中损坏，所以产品产率提高。

公开(公告)号：US20140154842A1

公开(公告)日：2014-06-05

申请号：US14174988

申请日：2014-02-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/56 ,  H01L21/78 ,  H01L21/673 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract translation: 半导体封装的制造方法包括以下步骤：提供在其表面上形成有凹部和释放层的载体; 在凹部中的脱模层上设置芯片; 在芯片和释放层上形成密封剂; 去除释放层和载体; 并在密封剂和芯片上形成电路结构。 凹部的设计有助于芯片对准以防止其移位，从而提高产品的可靠性。 还提供了通过制造方法制造的半导体封装。

公开(公告)号：US10049955B2

公开(公告)日：2018-08-14

申请号：US15497964

申请日：2017-04-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

公开(公告)号：US20160196990A1

公开(公告)日：2016-07-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。