公开(公告)号：US20170075065A1

公开(公告)日：2017-03-16

申请号：US15342669

申请日：2016-11-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kai-Fang Cheng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/132 ,  H01L21/56 ,  H01L21/48 ,  G02B6/136 ,  G02B6/122

CPC分类号： G02B6/132 ,  G02B6/122 ,  G02B6/136 ,  G02B6/138 ,  G02B2006/12104 ,  H01L21/48 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L29/06 ,  H01L2224/73204

摘要： A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer.

摘要翻译： 一种方法包括在衬底上形成平坦区域和沟槽区域，其中沟槽区域包括斜面和平坦的底部，在平坦底部和斜面的一部分上沉积反射层，在第一粘附促进层上方沉积 反应层，对第一粘合促进剂层施加第一固化过程，其中，在第一固化过程结束后，反射层和第一粘合促进剂层形成第一粘合界面，沉积沉积在第一粘合促进剂上的底部包层 将第二固化过程施加到底部包层以形成第二接合界面层，将芯层沉积在底部包层上并在芯层上沉积顶部覆层。

公开(公告)号：US20240088025A1

公开(公告)日：2024-03-14

申请号：US18519516

申请日：2023-11-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US20230253286A1

公开(公告)日：2023-08-10

申请号：US18302210

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L23/373 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/53295

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US20240332070A1

公开(公告)日：2024-10-03

申请号：US18349672

申请日：2023-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen Ju Wu ,  Kai-Fang Cheng ,  Cheng-Chin Lee ,  Hsiao-Kang Chang ,  Hsin-Yen Huang

IPC分类号： H01L21/768 ,  C23C16/455 ,  H01L23/532

CPC分类号： H01L21/76832 ,  C23C16/45553 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L23/53238

摘要： A method according to the present disclosure includes receiving a workpiece that includes a first conductive feature embedded in a first dielectric layer, selectively depositing a capping layer over the first conductive feature, depositing a first etch stop layer (ESL) over the capping layer, depositing a glue layer over the first ESL, depositing a second ESL over the glue layer, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer, and forming a second conductive feature in the opening. A density of the second ESL is greater than a density of the first ESL.

公开(公告)号：US12080650B1

公开(公告)日：2024-09-03

申请号：US18544100

申请日：2023-12-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kai-Fang Cheng ,  Hsiao-Kang Chang ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/373 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/53295 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/3735 ,  H01L23/5226 ,  H01L23/53238 ,  H01L21/7685

摘要： Contact structures and methods of forming the same are provided. A contact structure according to the present disclosure includes an etch stop layer (ESL), a first pillar feature and a second pillar feature disposed on the ESL, a metal feature disposed between the first pillar feature and the second pillar feature, the metal feature including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature, along the first sidewall, the bottom surface and the second sidewall of the metal feature, and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner that extends along the first sidewall of the metal feature.

公开(公告)号：US11923357B2

公开(公告)日：2024-03-05

申请号：US17151345

申请日：2021-01-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kai-Fang Cheng ,  Kuang-Wei Yang ,  Cherng-Shiaw Tsai ,  Hsiaokang Chang

IPC分类号： H01L23/14 ,  H01L23/538 ,  H01L25/065 ,  H01L27/06

CPC分类号： H01L27/0688 ,  H01L23/147 ,  H01L23/5385 ,  H01L25/0657

摘要： An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

公开(公告)号：US10163797B2

公开(公告)日：2018-12-25

申请号：US14879259

申请日：2015-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Lin Teng ,  Jung-Hsun Tsai ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L23/485 ,  H01L29/78

摘要： A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

公开(公告)号：US11848198B2

公开(公告)日：2023-12-19

申请号：US17460798

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kai-Fang Cheng ,  Ting-Ya Lo ,  Hsiao-Kang Chang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/02115 ,  H01L21/31138 ,  H01L21/76832

摘要： A method for manufacturing a semiconductor device having a low-k carbon-containing dielectric layer includes: depositing a low-k carbon-containing dielectric material, which has a carbon content ranging from 16 atomic % to 23 atomic %, using a precursor mixture to form a carbon-containing dielectric layer having a k value ranging from 2.8 to 3.3 and a porosity ranging from 0.03% to 1.0%; forming the carbon-containing dielectric layer into a patterned carbon-containing dielectric layer having a recess therein by etching, the patterned carbon-containing dielectric layer having a porosity ranging from 1.0% to 2.0%; and filling the recess with an electrically conductive material to form an electrically conductive feature in the patterned carbon-containing dielectric layer.

公开(公告)号：US11830808B2

公开(公告)日：2023-11-28

申请号：US17739384

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US20220262726A1

公开(公告)日：2022-08-18

申请号：US17739384

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.