公开(公告)号：US11742265B2

公开(公告)日：2023-08-29

申请号：US16660713

申请日：2019-10-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hung-Yu Chou ,  Chi-Chen Chien ,  Yuh-Harng Chien ,  Steven Alfred Kummerl ,  Bo-Hsun Pan ,  Fu-Hua Yu

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/49548 ,  H01L23/49861 ,  H01L23/5228

Abstract: In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.

公开(公告)号：US11081428B2

公开(公告)日：2021-08-03

申请号：US16537535

申请日：2019-08-10

Applicant: Texas Instruments Incorporated

Inventor： Stanley Chou ,  Yuh-Harng Chien ,  Steven Alfred Kummerl ,  Bo-Hsun Pan ,  Pi-Chiang Huang ,  Frank Yu ,  Chih-Chien Ho

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/492

Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.

公开(公告)号：US11862538B2

公开(公告)日：2024-01-02

申请号：US17463124

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chung-Hao Lin ,  Hung-Yu Chou ,  Bo-Hsun Pan ,  Dong-Ren Peng ,  Pi-Chiang Huang ,  Yuh-Harng Chien

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2924/181

Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.

公开(公告)号：US20230005874A1

公开(公告)日：2023-01-05

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US11848297B2

公开(公告)日：2023-12-19

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48138 ,  H01L2224/48245 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48481 ,  H01L2224/85035 ,  H01L2224/85051 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US11735506B2

公开(公告)日：2023-08-22

申请号：US16206640

申请日：2018-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hung-Yu Chou ,  Bo-Hsun Pan ,  Yuh-Harng Chien ,  Fu-Hua Yu ,  Steven Alfred Kummerl ,  Jie Chen ,  Rajen M. Murugan

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503

Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

公开(公告)号：US20220336331A1

公开(公告)日：2022-10-20

申请号：US17229955

申请日：2021-04-14

Applicant: Texas Instruments Incorporated

Inventor： Chih-Chien Ho ,  Bo-Hsun Pan ,  Yuh-Harng Chien

IPC: H01L23/495 ,  H01L21/50

Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.

公开(公告)号：US20240274569A1

公开(公告)日：2024-08-15

申请号：US18617449

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bo-Hsun Pan ,  Hung-Yu Chou ,  Chung-Hao Lin ,  Yuh-Harng Chien

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/28

CPC classification number: H01L24/48 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/28 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/48177

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

公开(公告)号：US11942448B2

公开(公告)日：2024-03-26

申请号：US17377719

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bo-Hsun Pan ,  Hung-Yu Chou ,  Chung-Hao Lin ,  Yuh-Harng Chien

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L24/48 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/28 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/48177

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

公开(公告)号：US20230016577A1

公开(公告)日：2023-01-19

申请号：US17377719

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bo-Hsun Pan ,  Hung-Yu Chou ,  Chung-Hao Lin ,  Yuh-Harng Chien

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/28

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.