公开(公告)号：US20160043236A1

公开(公告)日：2016-02-11

申请号：US14923125

申请日：2015-10-26

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/808 ,  H01L21/32 ,  H01L21/266 ,  H01L27/098 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/808 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/32 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/36 ,  H01L29/66901

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

公开(公告)号：US20150179452A1

公开(公告)日：2015-06-25

申请号：US14572936

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L21/225 ,  H01L21/266 ,  H01L29/06 ,  H01L27/098 ,  H01L21/8232

CPC classification number: H01L29/808 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/32 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/36 ,  H01L29/66901

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移层的JFET和掩埋沟道，其中通过分段注入区域注入形成掩埋沟道，使得掩埋沟道的掺杂密度在掺杂密度的25％至50％之间 的埋层漂移层。

公开(公告)号：US20150097230A1

公开(公告)日：2015-04-09

申请号：US14044915

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract translation: 具有垂直漏极延伸MOS晶体管的半导体器件可以通过形成深沟槽结构以形成晶体管的垂直漂移区域而形成，使得每个垂直漂移区域通过深沟槽结构在至少两个相对侧上界定。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。 在垂直漂移区域上的衬底中的沟槽中形成沟槽栅极。 身体区域位于垂直漂移区域上的衬底中。

公开(公告)号：US20170084737A1

公开(公告)日：2017-03-23

申请号：US15364817

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/324 ,  H01L29/36 ,  H01L21/266 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

公开(公告)号：US20160300946A1

公开(公告)日：2016-10-13

申请号：US15182658

申请日：2016-06-15

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

公开(公告)号：US20150349092A1

公开(公告)日：2015-12-03

申请号：US14821085

申请日：2015-08-07

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

公开(公告)号：US20150179793A1

公开(公告)日：2015-06-25

申请号：US14559239

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/225 ,  H01L29/10 ,  H01L21/324 ,  H01L21/266 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract translation: 一种集成电路，其包含延伸漏极MOS晶体管，其具有漂移层，在上部RESURF层上并接触漂移层的上表面，以及在漂移层下面的埋入漏极延伸层，该漏极延伸层与漏极的漂移层电连接 在通道端处与漂移层分离。 可以在通道端处的漂移层和埋漏极延伸部之间形成较低的RESURF层。 上部RESURF层，漂移层，下部RESURF层和掩埋漏极延伸中的任何一个可以具有从漏极端到沟道端的渐变掺杂密度。 形成包含具有漂移层的延伸漏极MOS晶体管的集成电路的工艺，上部RESURF层和掩埋漏极延伸。

公开(公告)号：US20150145036A1

公开(公告)日：2015-05-28

申请号：US14559390

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw KOCON ,  Marie DENISON ,  Taylor Efland

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

Abstract translation: 一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。 源接触金属设置在身体区域和源区域上。 一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。 源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。

公开(公告)号：US20240304719A1

公开(公告)日：2024-09-12

申请号：US18667032

申请日：2024-05-17

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/42368 ,  H01L29/4238

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20180240870A1

公开(公告)日：2018-08-23

申请号：US15955122

申请日：2018-04-17

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40 ,  H01L21/225 ,  H01L29/10 ,  H01L21/324 ,  H01L21/761 ,  H01L29/423 ,  H01L21/266

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.