公开(公告)号：US11728406B2

公开(公告)日：2023-08-15

申请号：US17121343

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/3205 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/0262 ,  H01L21/02359 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02645 ,  H01L21/02664 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US11677015B2

公开(公告)日：2023-06-13

申请号：US17109895

申请日：2020-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Chiu ,  Yi Che Chan ,  Lun-Kuang Tan ,  Zheng-Yang Pan ,  Cheng-Po Chau ,  Pin-Ju Liang ,  Hung-Yao Chen ,  De-Wei Yu ,  Yi-Cheng Li

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66818 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

公开(公告)号：US20250079162A1

公开(公告)日：2025-03-06

申请号：US18952021

申请日：2024-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US10157770B2

公开(公告)日：2018-12-18

申请号：US15660107

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/70 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.

公开(公告)号：US20230352563A1

公开(公告)日：2023-11-02

申请号：US18342146

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/3205 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/32137 ,  H01L27/0924 ,  H01L21/02645 ,  H01L21/32055 ,  H01L21/02359 ,  H01L21/823864 ,  H01L21/823821 ,  H01L21/02664

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US11450555B2

公开(公告)日：2022-09-20

申请号：US17200198

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches.

公开(公告)号：US20210134984A1

公开(公告)日：2021-05-06

申请号：US17121343

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/3205 ,  H01L21/8238

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US10950490B2

公开(公告)日：2021-03-16

申请号：US16222769

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.

公开(公告)号：US10714348B2

公开(公告)日：2020-07-14

申请号：US16568585

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US11923235B2

公开(公告)日：2024-03-05

申请号：US17877824

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/785 ,  H01L27/105 ,  H01L27/1463

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.