公开(公告)号：US20250056851A1

公开(公告)日：2025-02-13

申请号：US18928641

申请日：2024-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hong Chang ,  Yi-Hsiu Liu ,  You-Ting Lin ,  Chih-Chung Chang ,  Kuo-Yi Chao ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Sung-En Lin ,  Chia-Cheng Chao ,  Chung-Ting Ko

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/786

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

公开(公告)号：US20240379348A1

公开(公告)日：2024-11-14

申请号：US18781257

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/383 ,  H01L21/443 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.

公开(公告)号：US20240363349A1

公开(公告)日：2024-10-31

申请号：US18771311

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/0338 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/66795

Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.

公开(公告)号：US12062578B2

公开(公告)日：2024-08-13

申请号：US17838645

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L27/01 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US11855185B2

公开(公告)日：2023-12-26

申请号：US17198133

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/02178 ,  H01L21/0332 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/66636 ,  H01L29/785

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230395702A1

公开(公告)日：2023-12-07

申请号：US18364352

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/785 ,  H01L21/02178 ,  H01L21/0332 ,  H01L29/66636

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230223304A1

公开(公告)日：2023-07-13

申请号：US17662940

申请日：2022-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/823418 ,  H01L21/31116 ,  H01L29/42392 ,  H01L21/823437 ,  H01L21/823468

Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.

公开(公告)号：US11532628B2

公开(公告)日：2022-12-20

申请号：US17325859

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Chung-Ting Ko ,  Wan Chen Hsieh ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US11441221B2

公开(公告)日：2022-09-13

申请号：US17018797

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Chung-Ting Ko ,  Tsung-Hsun Yu ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/033 ,  C23C16/455 ,  C23C16/40 ,  H01L21/8238

Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

公开(公告)号：US11296198B2

公开(公告)日：2022-04-05

申请号：US16838160

申请日：2020-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Chung-Ting Ko ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Tai-Chun Huang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3115

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.