公开(公告)号：US11011649B2

公开(公告)日：2021-05-18

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/426 ,  H01L27/12 ,  H01L29/49

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US20180331233A1

公开(公告)日：2018-11-15

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L21/426 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/426 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US20170110192A1

公开(公告)日：2017-04-20

申请号：US15382755

申请日：2016-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: G11C14/00 ,  H01L49/02 ,  H01L29/04 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66 ,  H01L27/108

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

公开(公告)号：US20170098599A1

公开(公告)日：2017-04-06

申请号：US14873189

申请日：2015-10-01

Applicant: United Microelectronics Corp.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L23/498 ,  H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L27/12 ,  H01L21/48 ,  H01L29/786

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5385 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. An interposer substrate is provided. At least one oxide semiconductor transistor is formed on the interposer substrate. At least one trough silicon via (TSV) is formed in the interposer substrate. An interconnection structure on the interposer substrate, and the at least one oxide semiconductor transistor is connected to the interconnection structure.

公开(公告)号：US09564217B1

公开(公告)日：2017-02-07

申请号：US14886116

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: H01L27/10 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  G11C14/00 ,  H01L29/786 ,  H01L27/108 ,  H01L27/105

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.

Abstract translation: 半导体存储器件包括具有主表面的半导体衬底，在半导体衬底的主表面上的至少第一电介质层，设置在第一介电层上的第一OS FET器件和第二OS FET器件，至少第二 覆盖第一电介质层的介质层，第一OS FET器件和第二OS FET器件，第二介电层上的第一MIM电容器，并且电耦合到第一OS FET器件;以及第二MIM电容器， 并电耦合到第二OS FET器件。

公开(公告)号：US20160322502A1

公开(公告)日：2016-11-03

申请号：US14724799

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

Abstract translation: 半导体结构包括基板和设置在基板中并沿着第一方向布置的第一元件。 第一元件由半导体氧化物材料制成。 半导体结构还包括设置在第一元件上的电介质层和设置在电介质层上并沿着第一方向布置的第二元件。 第二个元件用作晶体管结构的栅极。

公开(公告)号：US20160163693A1

公开(公告)日：2016-06-09

申请号：US14588991

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/10 ,  H01L28/87 ,  H01L28/91

Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.

Abstract translation: 提供具有电感器和MIM电容器的结构。 该结构包括电介质层，电感器和MIM电容器。 电感器和MIM电容器设置在电介质层内。 电感器包括芯和围绕芯的导线。 MIM电容器包括顶电极，底电极和绝缘层。 顶部电极或底部电极包括形成芯的材料。

公开(公告)号：US10475932B2

公开(公告)日：2019-11-12

申请号：US15828060

申请日：2017-11-30

Applicant: United Microelectronics Corp.

Inventor： Shao-Hui Wu ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8258

Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.

公开(公告)号：US20190027589A1

公开(公告)日：2019-01-24

申请号：US15655881

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/465

CPC classification number: H01L29/66969 ,  H01L21/465 ,  H01L29/7869

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

公开(公告)号：US10102907B2

公开(公告)日：2018-10-16

申请号：US15382755

申请日：2016-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: H01L27/108 ,  H01L29/786 ,  G11C14/00 ,  H01L49/02 ,  H01L27/12 ,  H01L21/02

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.