公开(公告)号：US20210265376A1

公开(公告)日：2021-08-26

申请号：US16798126

申请日：2020-02-21

Applicant: United Microelectronics Corp.

Inventor： CHIA-CHING HSU ,  Wang Xiang ,  Shen-De Wang ,  Chun-Sung Huang

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/792 ,  H01L21/765 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

公开(公告)号：US11011535B1

公开(公告)日：2021-05-18

申请号：US16724365

申请日：2019-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L29/51 ,  H01L21/311

Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

公开(公告)号：US20200373164A1

公开(公告)日：2020-11-26

申请号：US16417542

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEI XU ,  WENBO DING ,  Yu-Yang Chen ,  Wang Xiang

IPC: H01L21/28 ,  H01L27/11563 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

公开(公告)号：US20240315017A1

公开(公告)日：2024-09-19

申请号：US18135712

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEICHANG LIU ,  Wang Xiang ,  CHIA CHING HSU ,  Yung-Lin Tseng ,  Shen-De Wang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L28/20 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.

公开(公告)号：US20240292765A1

公开(公告)日：2024-08-29

申请号：US18658937

申请日：2024-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line directly on a first metal structure, a top electrode island disposed beside the bottom electrode line, a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island, and a cap layer covering a portion of the first metal structure and under the bottom electrode line.

公开(公告)号：US20220246845A1

公开(公告)日：2022-08-04

申请号：US17196979

申请日：2021-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H01L45/00 ,  H01L27/24

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.

公开(公告)号：US10916634B2

公开(公告)日：2021-02-09

申请号：US16417542

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Xu ,  Wenbo Ding ,  Yu-Yang Chen ,  Wang Xiang

IPC: H01L21/28 ,  H01L27/11563 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

公开(公告)号：US20240155843A1

公开(公告)日：2024-05-09

申请号：US17994401

申请日：2022-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  CHIA CHING HSU ,  Shen-De Wang ,  Yung-Lin Tseng ,  WEICHANG LIU

IPC: H10B43/35 ,  H10B41/23 ,  H10B41/35 ,  H10B43/23

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/1158

Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

公开(公告)号：US11127752B2

公开(公告)日：2021-09-21

申请号：US16798126

申请日：2020-02-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang ,  Chun-Sung Huang

IPC: H01L21/00 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L21/765 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

公开(公告)号：US20210233924A1

公开(公告)日：2021-07-29

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3213 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.