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39 条记录 (耗时 0.018 秒)

    Isolation boundaries in flash memory cores
    2.
    发明授权
    Isolation boundaries in flash memory cores 失效
    闪存内核中的隔离边界

    公开(公告)号：US06040597A

    公开(公告)日：2000-03-21

    申请号：US23166

    申请日：1998-02-13

    申请人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

    发明人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

    IPC分类号： H01L21/762 ,  H01L29/788

    CPC分类号： H01L21/76232 ,  H01L21/76237

    摘要： A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

    摘要翻译： 用于在闪速存储器芯晶片中建立隔离槽的湿蚀刻工艺包括在晶片的硅衬底上沉积氮化物和/或氧化物层，在其上沉积光致抗蚀剂层，然后将光致抗蚀剂层的预定部分暴露于紫外光以建立 在光致抗蚀剂层中的期望的凹槽图案。 然后使用干蚀刻工艺去除光致抗蚀剂层的凹槽图案下方的氮化物和/或氧化物层，从而暴露衬底的部分。 接下来，将晶片设置在诸如氢氧化钾的湿蚀刻溶液中，以在硅衬底的暴露部分中形成凹槽。 晶片被定向并适当地设置在浴中以形成V形槽，使得在蚀刻之后，槽的成角度的壁可以容易地暴露于直接在晶片上方的掺杂剂束，而不必使晶片或光束倾斜 资源。 因此，槽的壁容易用掺杂剂注入。

    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
    3.
    发明授权
    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
    非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间

    公开(公告)号：US06664191B1

    公开(公告)日：2003-12-16

    申请号：US09973131

    申请日：2001-10-09

    申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    IPC分类号： H01L21302

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

    摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

    摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

    System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device
    7.
    发明授权
    System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
    用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法

    公开(公告)号：US08759894B1

    公开(公告)日：2014-06-24

    申请号：US11189765

    申请日：2005-07-27

    申请人： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

    发明人： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/66833

    摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.

    摘要翻译： 提供了包括基板的存储器件。 第一电介质层形成在衬底上。 在衬底和第一介电层的一部分中形成隔离沟槽。 在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。 在所述至少两个电荷存储元件上形成第二电介质层。 控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度 所述至少两个电荷存储元件和所述控制栅极层。

    Method and system for providing a contact on a semiconductor device
    9.
    发明授权
    Method and system for providing a contact on a semiconductor device 失效
    用于在半导体器件上提供接触的方法和系统

    公开(公告)号：US6103593A

    公开(公告)日：2000-08-15

    申请号：US23836

    申请日：1998-02-13

    申请人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    发明人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/76237 ,  H01L21/76834 ,  Y10S438/97

    摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.

    摘要翻译： 公开了一种在半导体上提供至少一个接触的方法。 半导体包括多个隔离结构。 该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。 在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。