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    POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS
    1.
    发明申请
    POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS 有权
    集成电路电源管理系统

    公开(公告)号：US20160134289A1

    公开(公告)日：2016-05-12

    申请号：US14539697

    申请日：2014-11-12

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: H03K19/177 ,  H03K19/0175

    CPC classification number: H03K19/17772 ,  H03K19/00384 ,  H03K19/017509 ,  H03K19/17784

    Abstract: An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.

    Abstract translation: 一种装置包括多个可编程硬件资源和设置在IC芯片上的模数转换器（ADC）。 ADC被配置为量化IC芯片的一个或多个模拟参数的值。 该装置还包括配置控制电路，配置为响应于一组配置数据对可编程硬件资源进行编程。 可编程硬件资源被编程为实现由配置数据指定的一组电路，并将ADC连接到IC芯片的相应节点，以对模拟参数进行采样。 该装置还包括耦合到ADC并被配置为基于来自ADC的一个或多个模拟参数的量化值产生控制信号的接口电路。 接口电路将控制信号输出到耦合到IC芯片的电源端子的电源。

    Integration of a programmable device and a processing system in an integrated circuit package
    3.
    发明授权
    Integration of a programmable device and a processing system in an integrated circuit package 有权

    公开(公告)号：US10573598B2

    公开(公告)日：2020-02-25

    申请号：US15719288

    申请日：2017-09-28

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea ,  Sundararajarao Mohan ,  Stephen M. Trimberger

    IPC: G06F15/78 ,  H01L23/538 ,  H01L23/50

    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

    Optical communication circuits
    4.
    发明授权
    Optical communication circuits 有权

    公开(公告)号：US10476598B1

    公开(公告)日：2019-11-12

    申请号：US15219005

    申请日：2016-07-25

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea ,  Stephen M. Trimberger

    IPC: H01L25/00 ,  H04B10/50 ,  H04B10/508

    Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals.

    Active interrupt handler performance monitoring in microprocessors
    5.
    发明授权
    Active interrupt handler performance monitoring in microprocessors 有权

    公开(公告)号：US10282326B1

    公开(公告)日：2019-05-07

    申请号：US14527659

    申请日：2014-10-29

    Applicant: Xilinx, Inc.

    Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Austin H. Lesea ,  Graham F. Schelle ,  Paul R. Schumacher

    IPC: G06F13/24 ,  G06F13/26

    Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

    Power distribution network IP block
    8.
    发明授权
    Power distribution network IP block 有权
    配电网IP块

    公开(公告)号：US09525423B1

    公开(公告)日：2016-12-20

    申请号：US14862962

    申请日：2015-09-23

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: H03K19/177 ,  G06F1/26 ,  G01R31/317 ,  G01R31/3185

    CPC classification number: H03K19/17772 ,  G01R31/318513 ,  G01R31/318516 ,  H03K19/17764 ,  H03K19/17784

    Abstract: A device comprises a semiconductor substrate, a programmable logic device on the semiconductor substrate, a power distribution network comprising at least one voltage regulator on the semiconductor substrate, and a power management bus for communication between the at least one voltage regulator and the programmable logic device. The programmable logic device comprises a processing module configured to perform a diagnostic analysis of the power distribution network.

    Abstract translation: 一种器件包括半导体衬底，半导体衬底上的可编程逻辑器件，包括半导体衬底上的至少一个电压调节器的配电网络和用于在至少一个电压调节器与可编程逻辑器件之间进行通信的电力管理总线 。 可编程逻辑器件包括被配置为执行配电网络的诊断分析的处理模块。

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