公开(公告)号：US10816598B1

公开(公告)日：2020-10-27

申请号：US16148371

申请日：2018-10-01

Applicant: Xilinx, Inc.

Inventor： Ushasri Merugu ,  Mahesh Sankroj ,  Sharat Babu Kotamraju

IPC: G01R31/317 ,  G06F1/08 ,  G01R31/3177

Abstract: A system for debugging circuits includes an integrated circuit configured to implement a circuit under test and a logic analyzer controller coupled to the circuit under test. The system includes a host computing system configured to communicate with the logic analyzer controller and provide a debug command to the logic analyzer controller. The logic analyzer controller, in response to the debug command, controls operation of the circuit under test.

公开(公告)号：US10062454B1

公开(公告)日：2018-08-28

申请号：US15372301

申请日：2016-12-07

Applicant: Xilinx, Inc.

Inventor： Ushasri Merugu ,  Mahesh Sankroj ,  Sudheer K. Koppolu ,  Siva V. N. Hemasunder Tallury

IPC: G11C29/52 ,  G06F1/12

CPC classification number: G11C29/52 ,  G06F1/12 ,  G11C7/222 ,  G11C29/023

Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.

公开(公告)号：US10235272B2

公开(公告)日：2019-03-19

申请号：US15451068

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Mahesh Sankroj ,  Nikhil A. Dhume ,  Kumar Deepak

IPC: G06F11/36 ,  G06F17/50 ,  G06F11/277 ,  G06F9/44

Abstract: An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

公开(公告)号：US20180253368A1

公开(公告)日：2018-09-06

申请号：US15451068

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Mahesh Sankroj ,  Nikhil A. Dhume ,  Kumar Deepak

IPC: G06F11/36 ,  G06F11/277

CPC classification number: G06F11/3636 ,  G06F11/277 ,  G06F11/3628 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F17/5027

Abstract: An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

公开(公告)号：US10161999B1

公开(公告)日：2018-12-25

申请号：US15091376

申请日：2016-04-05

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Niloy Roy ,  Mahesh Sankroj ,  Siddharth Rele ,  Riyas Noorudeen Remla ,  Rajesh Bansal ,  Bradley K. Fross

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

公开(公告)号：US10120831B1

公开(公告)日：2018-11-06

申请号：US15367611

申请日：2016-12-02

Applicant: Xilinx, Inc.

Inventor： Mahesh Sankroj ,  Jason Villarreal

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F13/40

Abstract: A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request.