公开(公告)号：US06754126B2

公开(公告)日：2004-06-22

申请号：US10106597

申请日：2002-03-27

申请人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

发明人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

摘要翻译： 形成多个第一存储块和用于再现第一存储块的数据的第二存储块。 当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。 当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。 因此，可以在不被用户识别的情况下进行刷新操作。 即，可以提供用户友好的半导体存储器。

公开(公告)号：US06429705B1

公开(公告)日：2002-08-06

申请号：US09820714

申请日：2001-03-30

申请人： Yoshihide Bando ,  Toshiya Uchida

发明人： Yoshihide Bando ,  Toshiya Uchida

IPC分类号： H03K17687

CPC分类号： H03K17/223 ,  H03K17/145

摘要： A resetting circuit includes first and second transistors that respectively receive first and second voltages through gates. The ratio W/L of the second transistor is larger than that of the first transistor. The first and second voltages rise in accordance with the rise of a supply voltage. The second voltage is lower than the first voltage. Since an increase in the current IDS of the first transistor is greater than an increase in the current IDS of the second transistor, an inversion occurs between the current IDSs of the first and second transistors by applying a predetermined supply voltage. Since a reset signal is generated when the values of the currents IDS of the first and second transistors cross, the reset signal can always be generated by the predetermined supply voltage, independent from the threshold voltage of the transistor.

摘要翻译： 复位电路包括分别通过门接收第一和第二电压的第一和第二晶体管。 第二晶体管的比率W / L大于第一晶体管的比率W / L。 第一和第二电压根据电源电压的上升而上升。 第二电压低于第一电压。 由于第一晶体管的电流IDS的增加大于第二晶体管的电流IDS的增加，所以通过施加预定的电源电压在第一和第二晶体管的电流IDS之间发生反转。 由于当第一和第二晶体管的电流IDS的值交叉时产生复位信号，所以与晶体管的阈值电压无关，总是可以通过预定的电源电压产生复位信号。

公开(公告)号：US4538126A

公开(公告)日：1985-08-27

申请号：US605655

申请日：1984-04-30

申请人： Yoshihide Bando

发明人： Yoshihide Bando

IPC分类号： H01F7/08 ,  H01H50/18 ,  H01H51/22 ,  H01H51/24 ,  H01H50/04

CPC分类号： H01H51/2227

摘要： An electromagnetic relay includes a coil wound around a core both of whose ends project therefrom. A yoke extends parallel thereto, and each of its ends is formed with two pole pieces which extend towards and lie one on each side of an end of the core with a certain gap being defined therebetween. A connecting member extends parallel to the core and the yoke and is mounted so as to be movable transversely, and means are provided for establishing and breaking some electrical connection according to such transverse movement. There are provided two armature pieces, one for each end of the core and both fixed to the connecting member. Each armature piece includes a permanent magnet plate and two plates of magnetic material fixed to it so as generally to form a C shape with one of the magnetic material plates being magnetized to be a north pole and the other a south pole. Each of the two plates of magnetic material is inserted on one side of an end of the core between it and the opposing one of the pole pieces of the yoke, into the gap therebetween. The directions of magnetization of the armature pieces are oppositely oriented. Thereby, when the relay switches over, it does so without generating any off center jerking, and thus its mounting to a base is improved. Also the quality of the magnetic circuit, and the manufacturability of the relay, are improved.

摘要翻译： 电磁继电器包括缠绕在其两端从其突出的芯的线圈。 磁轭平行于其延伸，并且每个端部形成有两个极片，两个极片在芯体的端部的每一侧延伸并且位于一个之间，其间限定一定间隙。 连接构件平行于铁芯和轭架延伸并且被安装成可横向移动，并且提供用于根据这种横向运动建立和断开一些电气连接的装置。 设置有两个电枢片，一个用于芯的每个端部，两个固定到连接构件。 每个电枢片包括永久磁铁板和固定在其上的两块磁性材料板，以大致形成C形，其中一个磁性材料板被磁化为北极，另一个为南极。 两个磁性材料板中的每一个插入到芯体的端部与磁轭的相对的一个极片之间的一端的两侧之间的间隙中。 电枢片的磁化方向相反取向。 因此，当继电器切换时，它不会产生任何偏心的冲击，从而提高了其安装到基座上。 此外，磁路的质量以及继电器的可制造性得到改善。

公开(公告)号：US07782124B2

公开(公告)日：2010-08-24

申请号：US11025047

申请日：2004-12-30

申请人： Yoshihide Bando

发明人： Yoshihide Bando

IPC分类号： G05F3/02

CPC分类号： H03K19/0016

摘要： The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

摘要翻译： 本发明的目的是减少使用MOS晶体管的电压供给电路的漏电流。 该电压供给电路包括其漏极连接到电源电压的阈值电压低的n沟道MOS晶体管和源极连接到n沟道MOS晶体管的p沟道MOS晶体管， 并且从漏极向负载电路提供电压vii。 由于当所述电路处于待机状态时，对p沟道MOS晶体管的栅极源施加电压V gs = 1V，所以p沟道MOS晶体管在比普通截止区域更大的截止区域工作 。

公开(公告)号：US6031788A

公开(公告)日：2000-02-29

申请号：US207335

申请日：1998-12-08

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G06F1/04 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.

摘要翻译： 当半导体集成电路处于有功掉电状态时，半导体集成电路适于使外部提供给半导体集成电路的外部时钟无效。 半导体集成电路包括延迟锁定环DLL电路，其输出与外部时钟同步的内部时钟。 锁存电路保持与DLL电路的内部时钟输出同步的控制信号。 内部电路基于从锁存电路提供的控制信号执行预定处理。

公开(公告)号：US4496806A

公开(公告)日：1985-01-29

申请号：US529723

申请日：1983-09-06

申请人： Kozo Maenishi ,  Masaaki Adachi ,  Yoshihide Bando

发明人： Kozo Maenishi ,  Masaaki Adachi ,  Yoshihide Bando

IPC分类号： H01H50/10 ,  H01H50/14 ,  H01H50/64 ,  H01P1/12 ,  H01H15/00 ,  H01H9/00 ,  H01H51/00 ,  H01P1/10

CPC分类号： H01P1/125 ,  H01H50/14 ,  H01H50/10 ,  H01H50/646

摘要： A high frequency R-F switch includes a switch body or housing made from a conductive material or a non-conductive resin having a conductive layer plated on the body surfaces. The switching device includes a first external connector, a first conductor having a switching contact member connected to the first external connector for switching a connection with the switch contact member. A conductive housing supports the first conductor, a second external connector and second conductor. The switch body or housing is in electrical connection with the second external conductor.

摘要翻译： 高频R-F开关包括由导电材料制成的开关体或壳体或具有镀在体表上的导电层的非导电树脂。 开关装置包括第一外部连接器，第一导体，其具有连接到第一外部连接器的开关触点构件，用于切换与开关接触构件的连接。 导电壳体支撑第一导体，第二外部连接器和第二导体。 开关体或壳体与第二外部导体电连接。

公开(公告)号：US06987698B2

公开(公告)日：2006-01-17

申请号：US10289314

申请日：2002-11-07

申请人： Yoshihide Bando ,  Yoshimasa Yagishita

发明人： Yoshihide Bando ,  Yoshimasa Yagishita

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

摘要翻译： 存储单元阵列被划分成多个存储区域，每个存储器区域包括多个读出放大器，并且每个存储单元被建立为数据输入/输出的单元。 至少在存储单元阵列的操作期间，每两个存储区域之间形成虚拟区域，并且包括设置为预定电压的虚拟位线。 由于虚拟位线被布线在两个相邻的存储区域的位线之间，因此可以防止任何存储区域中的位线中的电压变化影响其它存储区域中的位线。 结果，可以防止半导体存储器的故障。

公开(公告)号：US06288585B1

公开(公告)日：2001-09-11

申请号：US09535745

申请日：2000-03-27

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

公开(公告)号：US4292613A

公开(公告)日：1981-09-29

申请号：US67225

申请日：1979-08-17

申请人： Yoshihide Bando ,  Toshiki Tanaka

发明人： Yoshihide Bando ,  Toshiki Tanaka

IPC分类号： H01H51/24 ,  H01H50/04 ,  H01H45/02 ,  H01H45/14

CPC分类号： H01H50/043 ,  H01H50/04

摘要： An electromagnetic relay comprising a flat electromagnet, a movable plate member having on a lower surface a plurality of projections and a contact circuit device as stacked up together, said contact circuit device including a plurality of contact switching members each of which consists of a single movable blade and a single stationary contact, said movable blade being biased by the projections in accordance with their movement so as to provide a switching operation in cooperation with the corresponding stationary contact.

摘要翻译： 一种电磁继电器，包括平面电磁体，在下表面上具有多个突起的可动板构件和堆叠在一起的接触电路装置，所述接触电路装置包括多个触点切换构件，每个触点切换构件由单个可移动的 刀片和单个固定触点，所述可动刀片根据它们的运动被突起偏压，以便与相应的固定触点配合提供切换操作。

公开(公告)号：US20060049860A1

公开(公告)日：2006-03-09

申请号：US11025047

申请日：2004-12-30

申请人： Yoshihide Bando

发明人： Yoshihide Bando

IPC分类号： H03L7/00 ,  G05F1/10 ,  H03K17/687 ,  H03K3/286 ,  H03K3/356 ,  H03L7/06

CPC分类号： H03K19/0016

摘要： The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

摘要翻译： 本发明的目的是减少使用MOS晶体管的电压供给电路的漏电流。 该电压供给电路包括其漏极连接到电源电压的阈值电压低的n沟道MOS晶体管和源极连接到n沟道MOS晶体管的p沟道MOS晶体管， 并且从漏极向负载电路提供电压vii。 由于当所述电路处于待机状态时，对p沟道MOS晶体管的栅极源施加电压V gs = 1V，所以p沟道MOS晶体管在比普通截止区域更大的截止区域工作 。