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公开(公告)号:US20120153367A1
公开(公告)日:2012-06-21
申请号:US13316308
申请日:2011-12-09
申请人: Masanori Ogura , Hideo Kobayashi , Yukihiro Kuroda
发明人: Masanori Ogura , Hideo Kobayashi , Yukihiro Kuroda
IPC分类号: H01L29/772
CPC分类号: H01L23/522 , H01L23/5286 , H01L24/06 , H01L27/14603 , H01L2224/02166 , H01L2224/04042 , H01L2224/05548 , H01L2224/05567 , H01L2224/06151 , H01L2224/06155 , H01L2224/06159 , H01L2224/06165 , H01L2224/06169 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要: A power supply wiring and a pad are arranged on a first wiring layer. Then, the power supply wiring and the pad are arranged so as not to be mutually overlapped. Signal wirings are arranged on a second wiring layer. Another signal wiring is arranged on a layer different from the second wiring layer. The other signal wiring is arranged below the pad so as to be overlapped with the pad. The signal wirings and the other signal wiring are mutually connected by a plug. A buffer is arranged between the pad and the other signal wiring.
摘要翻译: 在第一布线层上布置有电源布线和焊盘。 然后,电源布线和垫被布置成不相互重叠。 信号布线布置在第二布线层上。 另一信号布线布置在不同于第二布线层的层上。 另一个信号线布置在垫的下方以与该垫重叠。 信号布线和其他信号布线通过插头相互连接。 缓冲器布置在焊盘和其他信号布线之间。
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公开(公告)号:US20230387054A1
公开(公告)日:2023-11-30
申请号:US18120866
申请日:2023-03-13
发明人: Junyoung KO
IPC分类号: H01L23/00
CPC分类号: H01L24/06 , H01L24/14 , H01L2224/04042 , H01L2224/02372 , H01L2224/0603 , H01L2224/06169 , H01L2224/1403 , H01L2224/14051 , H01L2224/1416
摘要: A semiconductor package is provided. The semiconductor package includes a substrate including first and second surfaces opposite to each other, a redistribution layer on the first surface and having third and fourth surfaces opposite to each other wherein the third surface of the redistribution layer faces the first surface, a semiconductor chip between the substrate and the redistribution layer, the semiconductor chip spaced apart from the first surface and electrically connected to the third surface, a connection structure between the substrate and the redistribution layer and horizontally spaced apart from the semiconductor chip wherein the connection structure is electrically connected to the first surface and the third surface, and a dielectric layer between the substrate and the redistribution layer. The dielectric layer covers the semiconductor chip and the connection structure and extends between the semiconductor chip and the first surface.
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公开(公告)号:US09859204B2
公开(公告)日:2018-01-02
申请号:US15230889
申请日:2016-08-08
发明人: Myeong Soon Park , Hyunsoo Chung , Won-young Kim , Ae-nee Jang , Chanho Lee
CPC分类号: H01L23/50 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02371 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/05 , H01L2224/05553 , H01L2224/05555 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06151 , H01L2224/06152 , H01L2224/06155 , H01L2224/06156 , H01L2224/06159 , H01L2224/0616 , H01L2224/06165 , H01L2224/06169 , H01L2224/06177 , H01L2224/06181 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16227 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/0613
摘要: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.
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公开(公告)号:US20170084559A1
公开(公告)日:2017-03-23
申请号:US15230889
申请日:2016-08-08
发明人: Myeong Soon Park , Hyunsoo Chung , Won-young Kim , Ae-nee Jang , Chanho Lee
IPC分类号: H01L23/00
CPC分类号: H01L23/50 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02371 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/05 , H01L2224/05553 , H01L2224/05555 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06151 , H01L2224/06152 , H01L2224/06155 , H01L2224/06156 , H01L2224/06159 , H01L2224/0616 , H01L2224/06165 , H01L2224/06169 , H01L2224/06177 , H01L2224/06181 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16227 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/0613
摘要: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.
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公开(公告)号:US07834466B2
公开(公告)日:2010-11-16
申请号:US11957838
申请日:2007-12-17
申请人: Robert J. Wenzel , Trung Q Duong , Ilan Lidsky
发明人: Robert J. Wenzel , Trung Q Duong , Ilan Lidsky
CPC分类号: H01L24/06 , H01L24/05 , H01L24/13 , H01L2224/02379 , H01L2224/0401 , H01L2224/0612 , H01L2224/06165 , H01L2224/06168 , H01L2224/06169 , H01L2224/131 , H01L2924/014
摘要: A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.
摘要翻译: 一种结构包括半导体管芯,其具有在半导体管芯的表面上的管芯焊盘的布置。 第一排管芯焊盘由第一组四个焊盘组成,并沿第一方向延伸。 第二排管芯焊盘与第一行相邻并且由在第一方向上延伸的第二组四个焊盘组成。 第二行从第一行开始的第一个方向的第一个偏移开始。 第三排管芯焊盘与第二排相邻,并且包括在第一方向上延伸的第三组四个焊盘。 第三行从第二行开始的第一个方向的第二个偏移开始。 这允许相对容易地访问所有的管芯焊盘。
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公开(公告)号:US08581361B2
公开(公告)日:2013-11-12
申请号:US13316308
申请日:2011-12-09
申请人: Masanori Ogura , Hideo Kobayashi , Yukihiro Kuroda
发明人: Masanori Ogura , Hideo Kobayashi , Yukihiro Kuroda
IPC分类号: H01L29/00
CPC分类号: H01L23/522 , H01L23/5286 , H01L24/06 , H01L27/14603 , H01L2224/02166 , H01L2224/04042 , H01L2224/05548 , H01L2224/05567 , H01L2224/06151 , H01L2224/06155 , H01L2224/06159 , H01L2224/06165 , H01L2224/06169 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要: A power supply wiring and a pad are arranged on a first wiring layer. Then, the power supply wiring and the pad are arranged so as not to be mutually overlapped. Signal wirings are arranged on a second wiring layer. Another signal wiring is arranged on a layer different from the second wiring layer. The other signal wiring is arranged below the pad so as to be overlapped with the pad. The signal wirings and the other signal wiring are mutually connected by a plug. A buffer is arranged between the pad and the other signal wiring.
摘要翻译: 在第一布线层上布置有电源布线和焊盘。 然后,电源布线和垫被布置成不相互重叠。 信号布线布置在第二布线层上。 另一信号布线布置在不同于第二布线层的层上。 另一个信号线布置在垫的下方以与该垫重叠。 信号布线和其他信号布线通过插头相互连接。 缓冲器布置在焊盘和其他信号布线之间。
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公开(公告)号:US20090152718A1
公开(公告)日:2009-06-18
申请号:US11957838
申请日:2007-12-17
申请人: Robert J. Wenzel , Trung Q. Duong , Ilan Lidsky
发明人: Robert J. Wenzel , Trung Q. Duong , Ilan Lidsky
IPC分类号: H01L23/488
CPC分类号: H01L24/06 , H01L24/05 , H01L24/13 , H01L2224/02379 , H01L2224/0401 , H01L2224/0612 , H01L2224/06165 , H01L2224/06168 , H01L2224/06169 , H01L2224/131 , H01L2924/014
摘要: A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.
摘要翻译: 一种结构包括半导体管芯,其具有在半导体管芯的表面上的管芯焊盘的布置。 第一排管芯焊盘由第一组四个焊盘组成,并沿第一方向延伸。 第二排管芯焊盘与第一行相邻并且由在第一方向上延伸的第二组四个焊盘组成。 第二行从第一行开始的第一个方向的第一个偏移开始。 第三排管芯焊盘与第二排相邻,并且包括在第一方向上延伸的第三组四个焊盘。 第三行从第二行开始的第一个方向的第二个偏移开始。 这允许相对容易地访问所有的管芯焊盘。
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