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    Digital communication system
    3.
    发明授权
    Digital communication system 有权
    数字通讯系统

    公开(公告)号：US09548877B2

    公开(公告)日：2017-01-17

    申请号：US14654513

    申请日：2013-12-20

    申请人： University of South Australia

    发明人： Ingmar Rudiger Land ,  Gottfried Lechner ,  Alexander James Grant ,  David Victor Lawrie Haley

    IPC分类号： H04L27/20 ,  H04L27/18 ,  H04B10/516 ,  H03M13/00 ,  H03M13/29 ,  H03M13/37 ,  H03M13/11 ,  H04L1/00

    CPC分类号： H04L27/18 ,  H03M13/1157 ,  H03M13/1197 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3784 ,  H03M13/616 ,  H03M13/6325 ,  H03M13/6331 ,  H04B10/516 ,  H04L1/0042 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0065 ,  H04L27/2003

    摘要： Methods and apparatus for use in communication systems using recursive modulation schemes with a Low Density Generator Matrix code (including an irregular repeat accumulate (IRA) code) are described that have reduced complexity and thus reduced cost compared to prior art systems. A communication system is described in which the transmitter concatenates a low density generator matrix code with an accumulator followed by a recursive modulator in order to eliminate the use of an interleaver, and in which the receiver combines the decoder for the accumulator and the soft demodulator into a single joint decoder in order reduce the number of components and complexity. Another variation is also described in which the transmitter is further simplified by eliminated the accumulator altogether, and in which the receiver is further simplified by replacing the joint decoder with a soft demodulator prior to the LDGM soft decoder.

    摘要翻译： 使用具有低密度发生器矩阵码（包括不规则重复累积（IRA）码）的递归调制方案的通信系统中使用的方法和装置被描述为与现有技术系统相比降低了复杂度并因此降低了成本。 描述了一种通信系统，其中发射机将低密度发生器矩阵码与累加器后跟递归调制器连接，以消除交织器的使用，并且其中接收机将用于累加器的解码器和软解调器组合成 单个联合解码器，以减少组件的数量和复杂性。 还描述了另一变型，其中通过一起消除累加器来进一步简化发射机，并且其中通过在LDGM软解码器之前用软解调器替换联合解码器来进一步简化接收机。

    Method and apparatus for improved performance of iterative decoders on channels with memory
    4.
    发明授权
    Method and apparatus for improved performance of iterative decoders on channels with memory 有权
    用于改善具有存储器的通道上的迭代解码器性能的方法和装置

    公开(公告)号：US09438276B2

    公开(公告)日：2016-09-06

    申请号：US13674767

    申请日：2012-11-12

    申请人： Marvell International Ltd.

    发明人： Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

    IPC分类号： H03M13/00 ,  H03M13/11 ,  H03M13/29 ,  H03M13/39 ,  H03M13/41

    CPC分类号： H03M13/6331 ,  H03M13/1105 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/4138

    摘要： Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

    摘要翻译： 公开了用于改善具有存储器的各种通道上的迭代解码器的性能的系统和方法。 这些系统和方法可以减少迭代解码器不能产生与最初在通信或数据存储系统中发送的数据匹配的解码数据的情况的频率或数量。 迭代解码器包括SISO信道检测器和ECC解码器，并且按照常规解码模式中的至少一个迭代解码算法和/或错误恢复模式中的至少一个迭代解码算法解码编码信息。

    Systems and methods for data processing using global iteration result reuse
    8.
    发明授权
    Systems and methods for data processing using global iteration result reuse 有权
    使用全局迭代结果重用的数据处理系统和方法

    公开(公告)号：US09274889B2

    公开(公告)日：2016-03-01

    申请号：US13912059

    申请日：2013-06-06

    申请人： LSI Corporation

    发明人： Fan Zhang ,  Shu Li ,  Jun Xiao ,  Kaitlyn T. Nguyen

    IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/27 ,  H03M13/00 ,  H03M13/29

    CPC分类号： G06F11/1076 ,  H03M13/1111 ,  H03M13/27 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/6331 ,  H03M13/658 ,  H03M13/6583 ,  H04L2201/06

    摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. As an example, a data processing system is discussed that includes a data detector circuit operable to provide a first detector output and a second detector output, and a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output. The combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input.

    摘要翻译： 本发明涉及用于数据处理的系统和方法，更具体地涉及用于由数据解码器输出的检测器的系统和方法。 作为示例，讨论了包括可操作以提供第一检测器输出和第二检测器输出的数据检测器电路的数据处理系统，以及组合电路，其可操作以将从第一检测器输出导出的第一输入与导出的第二输入 从第二检测器输出产生组合的检测器输出。 组合的检测器输出包括通过将第一输入的元素与第二输入的相应元素组合而产生的统一数据集元素。

    LEH memory module architecture design in the multi-level LDPC coded iterative system
    9.
    发明授权
    LEH memory module architecture design in the multi-level LDPC coded iterative system 有权
    LEH存储器模块架构设计在多级LDPC编码迭代系统中

    公开(公告)号：US09219504B2

    公开(公告)日：2015-12-22

    申请号：US13663006

    申请日：2012-10-29

    申请人： LSI Corporation

    发明人： Zongwang Li ,  Lei Chen ,  Shaohua Yang ,  Johnson Yen

    IPC分类号： H03M13/00 ,  H03M13/27 ,  H03M13/11

    CPC分类号： H03M13/6505 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/6331

    摘要： A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.

    摘要翻译： LDPC解码系统中的存储器包括组织成乒乓存储器的数据库。 乒乓存储器连接到交织器和解交织器。 交织器交织L值; 然后将交错的L值存储在乒乓存储器中。 LDPC解码器从乒乓存储器检索L值并将E值返回给乒乓存储器。 解交织器对E值进行解交织，并将数据发送到LE队列和HD队列。