公开(公告)号：US20240420759A1

公开(公告)日：2024-12-19

申请号：US18815007

申请日：2024-08-26

Applicant: R&D 3 LLC

Inventor： Ravindraraj Ramaraju

IPC: G11C11/4096 ,  G11C11/405

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a data node, a first transistor, a second transistor, a third transistor, a write port for writing data to be stored in the memory cell, and a read port having a variable impedance that varies in accordance with a respective data value stored therein. The data value is one of at least three different data values that the memory cell is capable of storing. The second transistor and third transistor are coupled in series between the read port and a fixed reference. The first transistor is coupled between the write port and the data node.

公开(公告)号：US12156396B2

公开(公告)日：2024-11-26

申请号：US17424664

申请日：2019-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Tatsuya Onuki ,  Takahiko Ishizu ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H10B12/00 ,  G11C5/02 ,  H01L27/12 ,  H01L29/786 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

公开(公告)号：US12051457B2

公开(公告)日：2024-07-30

申请号：US17664465

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chieh Liu ,  Jui-Jen Wu ,  Win-San Khwa ,  Yi-Lun Lu ,  Meng-Fan Chang

IPC: G11C11/34 ,  G11C11/405

CPC classification number: G11C11/405

Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

公开(公告)号：US20240134605A1

公开(公告)日：2024-04-25

申请号：US18278451

申请日：2022-02-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/121

CPC classification number: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/1213 ,  H10K59/1216

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

公开(公告)号：US11963374B2

公开(公告)日：2024-04-16

申请号：US17582092

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H10B99/00 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/16 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B99/00 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/7833 ,  H10B12/00

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20240120340A1

公开(公告)日：2024-04-11

申请号：US18538161

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11501826B2

公开(公告)日：2022-11-15

申请号：US17105927

申请日：2020-11-27

Applicant: R&D 3 LLC

Inventor： Ravindraraj Ramaraju

IPC: G11C16/30 ,  G11C11/4096 ,  G11C5/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/56 ,  G11C7/14 ,  G11C11/404 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C8/16 ,  G11C11/405

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

公开(公告)号：US20220310148A1

公开(公告)日：2022-09-29

申请号：US17615867

申请日：2020-06-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: G11C11/405 ,  H03K3/012 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes a plurality of constant current circuits each given a digital signal. The constant current circuits each include a first transistor to a third transistor. The first transistor has a function of making a first current corresponding to set analog potential flow therethrough. The second transistor has a function of controlling the first current flowing between a source and a drain of the first transistor, in response to the digital signal. The third transistor has a function of holding the analog potential supplied to a gate of the first transistor, by being turned off. The first transistor to the third transistor each include a semiconductor layer including an oxide semiconductor in a channel formation region.

公开(公告)号：US20220209016A1

公开(公告)日：2022-06-30

申请号：US17694787

申请日：2022-03-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Kazuma FURUTANI

IPC: H01L29/786 ,  G11C5/06 ,  G11C11/405 ,  G11C11/4093 ,  G11C11/4096 ,  H01L27/108

Abstract: A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.

公开(公告)号：US20220172766A1

公开(公告)日：2022-06-02

申请号：US17602431

申请日：2020-04-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Toshiki HAMADA

IPC: G11C11/405 ,  G11C11/4091 ,  G11C11/56 ,  H01L29/786

Abstract: A semiconductor device storing data as a multilevel potential is provided. The semiconductor device includes a memory cell, first and second reference cells, first and second sense amplifiers, and first to third circuits. The first circuit has a function of outputting, to a first wiring and a third wiring, a first potential corresponding to a first signal output from the memory cell. The second circuit has a function of outputting, to a second wiring, a first reference potential corresponding to a second signal output from the first reference cell. The third circuit has a function of outputting, to the fourth wiring, a second reference potential corresponding to a third signal output from the second reference cell when a second switch is in an off state. The first sense amplifier refers to the first potential and the first reference potential and changes potentials of the first wiring and the second wiring. The second sense amplifier refers to the first potential and the second reference potential and changes potentials of the third wiring and the fourth wiring.