公开(公告)号：US20060261443A1

公开(公告)日：2006-11-23

申请号：US11133445

申请日：2005-05-20

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/76

CPC classification number: H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US20060067137A1

公开(公告)日：2006-03-30

申请号：US11216197

申请日：2005-09-01

Applicant: Florin Udrea ,  Gehan Amaratunga

Inventor： Florin Udrea ,  Gehan Amaratunga

IPC: G11C5/14

CPC classification number: H01L29/86 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0634 ,  H01L29/66325 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/78603 ,  H01L29/868 ,  H02M7/003

Abstract: A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in part over plural membranes. There are non-membrane regions between the membranes. The device has a low voltage terminal and a high voltage terminal. At least a portion of the low voltage terminal and at least a portion of the high voltage terminal are connected directly or indirectly to a respective one of the high voltage junctions. At least those portions of the high voltage terminal that are in direct or indirect contact with one of the high voltage junctions are located on or in a respective one of the plural membranes.

Abstract translation: 高电压/功率半导体器件具有至少一个有源区，其具有并联电连接的多个高电压结。 每个高电压接头的至少一部分位于相应的膜中或上，使得有源区至少部分地设置在多个膜上。 膜之间有非膜区。 该器件具有低电压端子和高压端子。 低电压端子的至少一部分和高电压端子的至少一部分直接或间接地连接到相应的一个高压接点。 至少与高压接点中的一个直接或间接接触的高压端子的那些部分位于多个膜中的相应的一个上或其中。

公开(公告)号：US07005678B2

公开(公告)日：2006-02-28

申请号：US10984953

申请日：2004-11-10

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L31/0312

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including a base substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are laminated in this order; a cell portion disposed in the semiconductor substrate and providing an electric part forming portion; and a periphery portion surrounding the cell portion. The periphery portion includes a trench, which penetrates the second and the third semiconductor layers, reaches the first semiconductor layer, and surrounds the cell portion so that the second and the third semiconductor layers are divided by the trench substantially. The periphery portion further includes a fourth semiconductor layer disposed on an inner wall of the trench.

Abstract translation: 碳化硅半导体器件包括：依次层叠的包括基底基板，第一半导体层，第二半导体层和第三半导体层的半导体基板; 设置在所述半导体衬底中并提供电气部件形成部分的单元部分; 以及围绕单元部分的周边部分。 周边部分包括穿透第二和第三半导体层的沟槽到达第一半导体层，并且围绕电池部分，使得第二和第三半导体层基本上被沟槽划分。 外围部分还包括设置在沟槽的内壁上的第四半导体层。

公开(公告)号：US06927102B2

公开(公告)日：2005-08-09

申请号：US10694736

申请日：2003-10-29

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L21/329 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/20 ,  H01L29/24 ,  H01L29/32 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L21/332

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US20050151158A1

公开(公告)日：2005-07-14

申请号：US10984953

申请日：2004-11-10

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/06 ,  H01L21/04 ,  H01L21/337 ,  H01L21/8232 ,  H01L27/06 ,  H01L29/24 ,  H01L29/808 ,  H01L29/15 ,  H01L21/332

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including a base substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are laminated in this order; a cell portion disposed in the semiconductor substrate and providing an electric part forming portion; and a periphery portion surrounding the cell portion. The periphery portion includes a trench, which penetrates the second and the third semiconductor layers, reaches the first semiconductor layer, and surrounds the cell portion so that the second and the third semiconductor layers are divided by the trench substantially. The periphery portion further includes a fourth semiconductor layer disposed on an inner wall of the trench.

Abstract translation: 碳化硅半导体器件包括：依次层叠的包括基底基板，第一半导体层，第二半导体层和第三半导体层的半导体基板; 设置在所述半导体衬底中并提供电气部件形成部分的单元部分; 以及围绕单元部分的周边部分。 周边部分包括穿透第二和第三半导体层的沟槽到达第一半导体层，并且围绕电池部分，使得第二和第三半导体层基本上被沟槽划分。 外围部分还包括设置在沟槽的内壁上的第四半导体层。

公开(公告)号：US5489787A

公开(公告)日：1996-02-06

申请号：US271407

申请日：1994-07-06

Applicant: Gehan A. Amaratunga ,  Florin Udrea

Inventor： Gehan A. Amaratunga ,  Florin Udrea

IPC: H01L29/74 ,  H01L27/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L31/111

CPC classification number: H01L29/7455 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/7397

Abstract: An insulated gate field effect device (1a,1b,1c,1d) has a semiconductor body (2) with a first region (3) of one conductivity type, a second region (4) of the opposite conductivity type, a third region (6) of the one conductivity type (7) separated from the first region (3) by the second region (4) and at least one injector region (8) for injecting charge carriers of the opposite conductivity type into the first region (3). The conduction channel area (40) adjoining the insulated gate (9, 10) has first and second subsidiary areas (40 and 40b) for providing respective first and second subsidiary conduction channels. The second subsidiary area (40b) is spaced from the third region (6) and is more lowly doped than the first subsidiary conduction channel area (40a) for causing, when the injected opposite conductivity current type reaches a given value, the pn junction (40b') between the second subsidiary channel (40b ) and the second region (4) to become forward-biassed causing the bipolar transistor formed by the second subsidiary channel (40b), the second region (4) and the first region (3) to conduct to initiate with the at least one injector region (8) thyristor action which ceases upon removal of the conduction channel.

Abstract translation: 绝缘栅场效应器件（1a，1b，1c，1d）具有半导体本体（2），具有一个导电类型的第一区域（3），具有相反导电类型的第二区域（4），第三区域 通过第二区域（4）与第一区域（3）分离的一个导电类型（7）的至少一个导电类型（7）的至少一个注入区域（8）和用于将相反导电类型的电荷载流子注入到第一区域（3）中的至少一个注入区域 。 与绝缘栅极（9,10）相邻的导电沟道区域（40）具有用于提供相应的第一和第二辅助导电沟道的第一和第二辅助区域（40和40b）。 第二辅助区域（40b）与第三区域（6）间隔开，并且比第一辅助导电通道区域（40a）更低掺杂，用于当注入的相反电导率电流类型达到给定值时，引起pn结（ 40b）和第二区域（4）之间的第二区域（4）和第二区域（4）之间，以使得由第二辅助通道（40b），第二区域（4）和第一区域（3）形成的双极晶体管 以便启动与去除导电通道时停止的至少一个注入器区域（8）晶闸管动作。