公开(公告)号：US08345479B2

公开(公告)日：2013-01-01

申请号：US13281591

申请日：2011-10-26

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

摘要翻译： 根据本发明的示例的三维堆叠的非易失性半导体存储器包括：存储单元阵列，包括在第一方向上并排设置的第一和第二块;以及驱动器，设置在第二个存储单元阵列的一端 方向与第一方向正交。 在第一块中的第一选择栅极线和第二块中的第一选择栅极线在其一端在存储单元阵列的第二方向上以一对一的关系共同连接之后连接到驱动器。

公开(公告)号：US20120320677A1

公开(公告)日：2012-12-20

申请号：US13420767

申请日：2012-03-15

申请人： Hiroshi MAEJIMA ,  Koji HOSONO

发明人： Hiroshi MAEJIMA ,  Koji HOSONO

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line.

摘要翻译： 在写入操作中，控制电路将多个位线之间的禁止写入位线的电压提高到第一电压，然后使写入禁止位线处于浮置状态。 然后，控制电路将写入禁止位线以外的写入位线的电压提高到第二电压。 以这种方式，控制电路禁止写入对应于禁止写入位线的存储晶体管。 另一方面，控制电路对与写入位线对应的存储晶体管执行写入。

公开(公告)号：US20120307562A1

公开(公告)日：2012-12-06

申请号：US13423518

申请日：2012-03-19

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/30

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10

摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor substrate; a memory cell array including a plurality of memory cells, the memory cells being stacked on the semiconductor substrate; and a power supply circuit provided on the semiconductor substrate. The power supply circuit includes: a pump circuit configured to generate a voltage and supply the voltage to the memory cell array; a limiter circuit configured to output control signal for activating the pump circuit according to a comparison result between a voltage value of the output terminal and a first value; a capacitor configured to adjust a voltage of the output terminal; a boost circuit configured to charge the capacitor using a constant current based on the control signal; and a switch configured to stop a charge operation of the boost circuit. The capacitor is provided directly below the memory cell array.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：半导体衬底; 包括多个存储单元的存储单元阵列，所述存储单元堆叠在所述半导体衬底上; 以及设置在半导体基板上的电源电路。 电源电路包括：泵电路，被配置为产生电压并将电压提供给存储单元阵列; 限制器电路，被配置为根据所述输出端子的电压值与第一值之间的比较结果来输出用于激活所述泵电路的控制信号; 电容器，被配置为调节所述输出端子的电压; 升压电路，被配置为基于所述控制信号使用恒定电流对所述电容器进行充电; 以及配置为停​​止升压电路的充电操作的开关。 电容器直接位于存储单元阵列的正下方。

公开(公告)号：US08300466B2

公开(公告)日：2012-10-30

申请号：US13037965

申请日：2011-03-01

申请人： Hiroshi Maejima ,  Katsuaki Isobe

发明人： Hiroshi Maejima ,  Katsuaki Isobe

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.

摘要翻译： 读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电 位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中 高于所述接地电位，并且等于或低于所述第二电压。

公开(公告)号：US20120201070A1

公开(公告)日：2012-08-09

申请号：US13415953

申请日：2012-03-09

申请人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire to a standby voltage larger than a reference voltage prior to programming a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying to the selected first wire a program voltage for programming of the selected variable resistor and applying to the non-selected second wire a control voltage which prevents the rectifying device from turning ON.

摘要翻译： 非易失性半导体存储装置包括第一和第二相交线; 在第一第二导线的交点设置有包含用于将电阻值作为数据非易失性地存储的可变电阻器和整流装置的电可重写存储单元串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。 在通过将参考电压提供给未选择的第一线和所选择的第二线之前，控制电路将未选择的第二线预充电至大于参考电压的待机电压，然后再对连接到所选择的第一和第二线的可变电阻进行编程， 向所选择的第一线施加用于对所选择的可变电阻器进行编程的编程电压，并向未选择的第二线施加防止整流装置导通的控制电压。

公开(公告)号：US20120163066A1

公开(公告)日：2012-06-28

申请号：US13414324

申请日：2012-03-07

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2213/72

摘要： A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell. When applying the control voltage plural times, the control circuit operates to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element from a high resistance state to a low resistance state. The control circuit operates to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value.

摘要翻译： 半导体存储装置包括：包括存储单元的存储单元阵列，每个存储单元具有可变电阻元件; 以及控制电路，被配置为将所述可变电阻元件所需的控制电压施加到选择的存储单元。 当多次施加控制电压时，控制电路操作以将在第一控制电压施加操作中施加的控制电压的值设置为基本上等于存储器中的所有存储器单元的电压值的分布的最小值 电池阵列需要将可变电阻元件的电阻状态从高电阻状态转移到低电阻状态。 控制电路通过将控制电压的值增加一定值来进行多个控制电压施加操作。

公开(公告)号：US20120105140A1

公开(公告)日：2012-05-03

申请号：US13342620

申请日：2012-01-03

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C16/30 ,  H02M2001/0025

摘要： The voltage generation circuit having a standard voltage generation circuit, a reference voltage, a minimum voltage setting circuit, and a voltage setting circuit that gradually sets voltage by switching a plurality of the gate transistors to switch a combination of resistive elements. The voltage generation circuit includes a differential amplifier that has one input terminal connected to the reference voltage generated by the standard voltage generation circuit and another input terminal connected to the minimum voltage setting circuit. The differential amplifier has an output node showing the result of a difference voltage of the inputs. The voltage generation circuit includes a pump control circuit that outputs a control signal controlling a charge-pump motion, based on the differential voltage, and a charge pump circuit that sets up and outputs the voltage by the control signal.

摘要翻译： 电压产生电路具有通过切换多个栅极晶体管来切换电阻元件的组合而逐渐设定电压的标准电压产生电路，参考电压，最小电压设定电路和电压设定电路。 电压产生电路包括差分放大器，其具有连接到由标准电压产生电路产生的参考电压的一个输入端子和连接到最小电压设置电路的另一个输入端子。 差分放大器具有显示输入的差分电压的结果的输出节点。 电压产生电路包括：泵控制电路，其基于差分电压输出控制电荷泵运动的控制信号;以及电荷泵电路，其通过控制信号建立和输出电压。

公开(公告)号：US20120039128A1

公开(公告)日：2012-02-16

申请号：US13281591

申请日：2011-10-26

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

摘要翻译： 根据本发明的示例的三维堆叠的非易失性半导体存储器包括：存储单元阵列，包括在第一方向上并排设置的第一和第二块;以及驱动器，其设置在第二个存储单元阵列的一端 方向与第一方向正交。 在第一块中的第一选择栅极线和第二块中的第一选择栅极线在其一端在存储单元阵列的第二方向上以一对一的关系共同连接之后连接到驱动器。

公开(公告)号：US08111536B2

公开(公告)日：2012-02-07

申请号：US12556299

申请日：2009-09-09

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C5/02 ,  G11C5/025 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72

摘要： The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first resistance value and a second resistance value higher than the first resistance value. The contact arrangement portion is formed to arrange a plurality of contacts on a plane. The contacts are connected to the first wirings or the second wirings. The probe can move along the plane to electrically contact with either of the contacts.

摘要翻译： 存储单元阵列具有各自位于多个第一布线和多个第二布线之间的相应交点处的存储单元。 每个存储单元具有串联连接的整流元件和可变电阻元件。 电阻元件可以具有比第一电阻值高的至少第一电阻值和第二电阻值。 接触布置部分形成为在平面上布置多个触点。 触点连接到第一布线或第二布线。 探头可以沿着平面移动以与任何一个触点电接触。

公开(公告)号：US08094501B2

公开(公告)日：2012-01-10

申请号：US12848762

申请日：2010-08-02

申请人： Hiroshi Maejima ,  Makoto Hamada

发明人： Hiroshi Maejima ,  Makoto Hamada

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26

摘要： A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.

摘要翻译： 半导体存储器件包括存储单元，源极线，字线，位线和驱动电路。 存储单元形成在半导体层上，并且在电荷累积层上具有电荷累积层和控制栅极。 字线连接到存储单元的门。 位线电连接到存储器单元的漏极。 源极线电连接到存储器单元的源极。 驱动器电路结合源极线的电位改变半导体层的电位。