Single-layered printed circuit board and manufacturing method thereof
    91.
    发明授权
    Single-layered printed circuit board and manufacturing method thereof 有权
    单层印刷电路板及其制造方法

    公开(公告)号:US08889994B2

    公开(公告)日:2014-11-18

    申请号:US13018971

    申请日:2011-02-01

    IPC分类号: H05K1/16

    摘要: A single layered printed circuit board and a method of manufacturing the same are disclosed. In accordance with an embodiment of the present invention, the method can include forming a bonding pad, a circuit pattern and a post on a surface of an insulation film, in which one end part of the post is electrically connected to at least a portion of the circuit pattern, pressing an insulator on the surface of the insulation film, in which the circuit pattern and the post are buried in the insulator, selectively etching the insulator such that the other end part of the post is exposed, and opening a portion of the insulation film such that at least a portion of the bonding pad is exposed.

    摘要翻译: 公开了一种单层印刷电路板及其制造方法。 根据本发明的实施例,该方法可以包括在绝缘膜的表面上形成焊盘,电路图案和柱,其中柱的一个端部电连接到绝缘膜的至少一部分 电路图案,将电路图案和柱埋在绝缘体中的绝缘膜表面上的绝缘体按压绝缘体,选择性地蚀刻绝缘体,使得柱的另一端暴露,并且打开一部分 所述绝缘膜使得所述焊盘的至少一部分露出。

    Methods of manufacturing semiconductor devices
    95.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号:US08431462B2

    公开(公告)日:2013-04-30

    申请号:US13183630

    申请日:2011-07-15

    摘要: A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively.

    摘要翻译: 一种制造半导体器件的方法包括在衬底上形成栅极结构; 形成牺牲隔离物可以形成在栅极衬底的侧壁上; 通过使用栅极结构和牺牲隔离物作为离子注入掩模的第一离子注入工艺将第一杂质注入到衬底的部分中以形成源区和漏区; 去除牺牲隔离物; 以及通过使用所述栅极结构作为离子注入掩模的第二离子注入工艺将第二杂质和碳原子注入到所述衬底的部分中,以分别形成源极和漏极延伸区域和碳掺杂区域。

    Method for manufacturing circuit board
    96.
    发明授权
    Method for manufacturing circuit board 失效
    电路板制造方法

    公开(公告)号:US08418355B2

    公开(公告)日:2013-04-16

    申请号:US11976071

    申请日:2007-10-19

    IPC分类号: H05K3/20

    摘要: A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.

    摘要翻译: 公开了一种形成转录电路的方法及其制造方法。 一种形成转录电路的方法,其包括通过在模板上选择性地形成抗蚀剂来形成对应于电路图案的凹版图案,将导电材料填充到凹版图案中,以及通过将载体压载到载体上而将载体转移到 使得载体面向具有填充有导电材料的模板的表面的模板,使得可以形成可以使用现有设备转录成绝缘板的转录电路,由此可以降低成本。

    Low density parity code encoding device and decoding device and encoding and decoding methods thereof
    97.
    发明授权
    Low density parity code encoding device and decoding device and encoding and decoding methods thereof 有权
    低密度奇偶校验码编码装置及解码装置及其编解码方法

    公开(公告)号:US08281206B2

    公开(公告)日:2012-10-02

    申请号:US12268534

    申请日:2008-11-11

    IPC分类号: H03M13/00

    摘要: A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix.

    摘要翻译: 提供了一种低密度奇偶校验码(LDPC)编码和解码装置及其编码和解码方法。 LDPC编码装置包括获取至少两个频带的状态信息的信息获取单元,基于状态信息生成奇偶校验矩阵的矩阵生成单元,所述奇偶校验矩阵包括对应于所述至少两个频带的子矩阵 频带,以及使用具有所生成的奇偶校验矩阵的LDPC生成数据位和奇偶校验位的编码器。

    SINGLE-LAYERED PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
    99.
    发明申请
    SINGLE-LAYERED PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 有权
    单层印刷电路板及其制造方法

    公开(公告)号:US20110186342A1

    公开(公告)日:2011-08-04

    申请号:US13018971

    申请日:2011-02-01

    IPC分类号: H05K1/11 H05K3/06

    摘要: A single layered printed circuit board and a method of manufacturing the same are disclosed. In accordance with an embodiment of the present invention, the method can include forming a bonding pad, a circuit pattern and a post on a surface of an insulation film, in which one end part of the post is electrically connected to at least a portion of the circuit pattern, pressing an insulator on the surface of the insulation film, in which the circuit pattern and the post are buried in the insulator, selectively etching the insulator such that the other end part of the post is exposed, and opening a portion of the insulation film such that at least a portion of the bonding pad is exposed.

    摘要翻译: 公开了一种单层印刷电路板及其制造方法。 根据本发明的实施例,该方法可以包括在绝缘膜的表面上形成焊盘,电路图案和柱,其中柱的一个端部电连接到绝缘膜的至少一部分 电路图案,将电路图案和柱埋在绝缘体中的绝缘膜表面上的绝缘体按压绝缘体,选择性地蚀刻绝缘体,使得柱的另一端暴露,并且打开一部分 所述绝缘膜使得所述焊盘的至少一部分露出。

    Non-volatile memory device and method of manufacturing the same
    100.
    发明授权
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号:US07972923B2

    公开(公告)日:2011-07-05

    申请号:US11605317

    申请日:2006-11-29

    IPC分类号: H01L21/336

    CPC分类号: H01L29/7881 H01L29/66825

    摘要: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

    摘要翻译: 半导体器件可以包括设置在衬底的有源区上的隧道绝缘层,设置在衬底的表面部分中以限定有源区的场绝缘图案,每个场绝缘图案具有形成在上表面部分的上凹部 设置在隧道绝缘层上的堆叠结构,以及设置在与堆叠结构相邻的有源区的表面部分处的杂质扩散区。