公开(公告)号：US08986555B2

公开(公告)日：2015-03-24

申请号：US12892047

申请日：2010-09-28

Applicant: Ji-Eun Kim ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

Inventor： Ji-Eun Kim ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

IPC: H01B13/00 ,  H05K3/40 ,  H05K3/06 ,  H05K3/20

CPC classification number: H05K3/4007 ,  H05K3/061 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2203/0152 ,  H05K2203/0376

Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.

Abstract translation: 公开了一种制造具有凸块的印刷电路板的方法。 该方法包括制备其上形成有第一电路的第一载体，将第一载体压缩到绝缘层的一个表面，使得第一电路被掩埋，根据凸点将在第一载体上堆叠抗蚀剂 通过蚀刻第一载体形成和形成凸块。 根据本发明的实施例，可以减小印刷电路板中的凸块与其相邻凸块之间的高度差，从而可以更好地实现电子部件和印刷电路板之间的电连接。

公开(公告)号：US08546943B2

公开(公告)日：2013-10-01

申请号：US12923037

申请日：2010-08-30

Applicant: Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L23/13 ,  H01L23/498

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract translation: 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。

公开(公告)号：US20110110058A1

公开(公告)日：2011-05-12

申请号：US12748082

申请日：2010-03-26

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

IPC: H05K7/02 ,  H05K3/00

CPC classification number: H05K3/00 ,  H01L2224/16225 ,  H05K3/30 ,  Y10T29/49124

Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component.

Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，片上封装衬底上的单层板包括形成在绝缘体上表面上的绝缘体，电路图案和倒装焊接焊盘，导体凸块， 与电路图案的下表面接触并穿透绝缘体，阻焊层，其形成在绝缘体的上表面上，使得至少一部分倒装芯片接合焊盘露出，并且 倒装芯片焊接凸块，其形成在倒装焊盘的上表面上，以便与电子部件进行倒装芯片连接。

公开(公告)号：US20110100952A1

公开(公告)日：2011-05-05

申请号：US12892047

申请日：2010-09-28

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

IPC: H05K3/06

CPC classification number: H05K3/4007 ,  H05K3/061 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2203/0152 ,  H05K2203/0376

Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.

Abstract translation: 公开了一种制造具有凸块的印刷电路板的方法。 该方法包括制备其上形成有第一电路的第一载体，将第一载体压缩到绝缘层的一个表面，使得第一电路被掩埋，根据凸点将在第一载体上堆叠抗蚀剂 通过蚀刻第一载体形成和形成凸块。 根据本发明的实施例，可以减小印刷电路板中的凸块与其相邻凸块之间的高度差，从而可以更好地实现电子部件和印刷电路板之间的电连接。

公开(公告)号：US20090011220A1

公开(公告)日：2009-01-08

申请号：US12153155

申请日：2008-05-14

Applicant: Jung-Hyun Park ,  Jeong-Woo Park ,  Sang-Duck Kim ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Jeong-Woo Park ,  Sang-Duck Kim ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

IPC: H05K1/05 ,  B29C65/42 ,  B32B7/00 ,  B32B7/12

CPC classification number: H05K3/205 ,  H05K3/108 ,  H05K3/4602 ,  H05K2203/1536 ,  Y10T428/249984 ,  Y10T428/31504 ,  Y10T428/31511 ,  Y10T428/3154 ,  Y10T428/31678 ,  Y10T428/31721 ,  Y10T428/31993

Abstract: A carrier and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing a printed circuit board may include: forming a first circuit pattern on each of a pair of release layers, which are attached respectively to either side of a base layer by adhesive layers; detaching the pair of release layers from the base layer; stacking and pressing the pair of release layers onto either side of an insulation substrate such that the first circuit patterns are buried in the insulation substrate; and separating the pair of release layers. By forming a circuit pattern on each of a pair of release layers with a single process, and transferring the circuit pattern into each side of an insulation substrate, the manufacturing process can be shortened and circuit patterns can be formed to a high density.

Abstract translation: 公开了载体和制造印刷电路板的方法。 制造印刷电路板的方法可以包括：在一对剥离层中的每一个上形成第一电路图案，其分别通过粘合剂层附着在基层的任一侧; 将一对释放层从基层分离; 堆叠并将一对释放层压在绝缘基板的任一侧上，使得第一电路图案被埋在绝缘基板中; 并分离一对释放层。 通过利用单一工艺在一对释放层的每一个上形成电路图案，并将电路图案转移到绝缘基板的每一侧，可以缩短制造工艺并且可以以高密度形成电路图案。

公开(公告)号：US20120244662A1

公开(公告)日：2012-09-27

申请号：US13491279

申请日：2012-06-07

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

IPC: H01L21/50

CPC classification number: H05K3/00 ,  H01L2224/16225 ,  H05K3/30 ,  Y10T29/49124

Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component.

Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，片上封装衬底上的单层板包括形成在绝缘体上表面上的绝缘体，电路图案和倒装焊接焊盘，导体凸块， 与电路图案的下表面接触并穿透绝缘体，阻焊层，其形成在绝缘体的上表面上，使得至少一部分倒装芯片接合焊盘露出，并且 倒装芯片焊接凸块，其形成在倒装焊盘的上表面上，以便与电子部件进行倒装芯片连接。

公开(公告)号：US20080251494A1

公开(公告)日：2008-10-16

申请号：US12078058

申请日：2008-03-26

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

IPC: H01B13/00 ,  C25D5/34

CPC classification number: C25D7/123 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/108

Abstract: A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.

Abstract translation: 公开了一种制造电路板的方法。 该方法可以包括：在层叠在载体上的金属层上形成与电路图案对应关系的释放图案; 将载体堆叠并压制到绝缘层上，其中减震图案面向绝缘层; 通过移除载体将金属层和释放图案转印到绝缘层中; 在所述绝缘层上形成通孔，所述绝缘层中所述金属层被转录到所述绝缘层上; 并通过在其上转印有金属层的绝缘层上进行电镀来填充通孔并在金属层上形成镀层。 由于可以在堆叠在载体上的金属层上形成缓和图案，并且可以将缓冲图案转录到绝缘层中，可以形成高密度电路图案。

公开(公告)号：US20070290344A1

公开(公告)日：2007-12-20

申请号：US11783871

申请日：2007-04-12

Applicant: Myung-Sam Kang ,  Byoung-Youl Min ,  Joon-Sung Kim ,  Je-Gwang Yoo ,  Jong-Gyu Choi

Inventor： Myung-Sam Kang ,  Byoung-Youl Min ,  Joon-Sung Kim ,  Je-Gwang Yoo ,  Jong-Gyu Choi

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. One aspect of present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a circuit pattern including bonding pads on one side of a first insulation layer, laminating a second insulation layer onto one side of the first insulation layer, and exposing the bonding pads by removing a part of the first insulation layer and the second insulation layer corresponding to the location in which the bonding pads is formed.

Abstract translation: 印刷电路板技术领域本发明涉及一种印刷电路板，特别涉及一种电子元件封装用印刷电路板及其制造方法。 本发明的一个方面提供了一种用于电子部件封装的印刷电路板的制造方法，其包括：形成包括在第一绝缘层的一侧上的焊盘的电路图案，将第二绝缘层层压到第一绝缘层的一侧上 绝缘层，并且通过去除与形成接合焊盘的位置相对应的第一绝缘层和第二绝缘层的一部分来暴露接合焊盘。

公开(公告)号：US20080102410A1

公开(公告)日：2008-05-01

申请号：US11976211

申请日：2007-10-22

Applicant: Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

Inventor： Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

IPC: G03C5/00

CPC classification number: H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/108 ,  H05K3/20 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/308 ,  H01L2224/0401

Abstract: A method of manufacturing a printed circuit board is disclosed, in which a cavity is formed for embedding a component, which includes: providing a core board, in which an inner circuit is buried; forming a first via in the core board for interlayer conduction; selectively forming a first photoresist in a position on the core board in correspondence with a position of the cavity; stacking a first build-up layer, on which a first outer circuit is formed, on the core board; and selectively removing the first build-up layer in correspondence with the position of the cavity and removing the first photoresist. Utilizing the method, a board can be manufactured with greater precision, as the thickness tolerance of the cavity may be obtained by controlling the thickness of the photoresist, and the overall thickness of the board can be controlled by controlling the height of the cavity.

Abstract translation: 公开了一种制造印刷电路板的方法，其中形成用于嵌入部件的空腔，其包括：提供其中埋入内部电路的芯板; 在芯板中形成层间导电的第一通孔; 在所述芯板上与所述腔的位置对应地选择性地形成第一光致抗蚀剂; 在芯板上堆叠形成有第一外部电路的第一堆积层; 并且与空腔的位置相对应地选择性地去除第一堆积层并除去第一光致抗蚀剂。 利用该方法，可以通过控制光致抗蚀剂的厚度来获得更高精度的板，因为通过控制光致抗蚀剂的厚度可以获得空腔的厚度公差，并且可以通过控制空腔的高度来控制板的整体厚度。

公开(公告)号：US20110095425A1

公开(公告)日：2011-04-28

申请号：US12923037

申请日：2010-08-30

Applicant: Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/50

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract translation: 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。