公开(公告)号：US20080242012A1

公开(公告)日：2008-10-02

申请号：US11729188

申请日：2007-03-28

Applicant: Sangwoo Pae ,  Jose Maiz ,  Gilbert Dewey ,  Matthew V. Metz ,  Markus Kuhn ,  Mark Doczy ,  Jack Kavalieros

Inventor： Sangwoo Pae ,  Jose Maiz ,  Gilbert Dewey ,  Matthew V. Metz ,  Markus Kuhn ,  Mark Doczy ,  Jack Kavalieros

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.

Abstract translation: 制造用于高k /金属栅极晶体管的高质量氮氧化硅层的方法包括在衬底上沉积高k电介质层，在高k电介质层上沉积阻挡层，其中阻挡层至少包括 氮气或氧气中的一种，在阻挡层上沉积覆盖层，并且在使阻挡层中的氮和/或氧的至少一部分扩散到高k电介质 层和基底。 扩散的氮或氧在界面处形成高质量的氮氧化硅层。 然后可以蚀刻高k电介质层，阻挡层和覆盖层以形成用于高k /金属栅极晶体管的栅极堆叠。 使用替代金属浇口工艺可以用金属栅电极代替覆盖层。

公开(公告)号：US20080224235A1

公开(公告)日：2008-09-18

申请号：US11724569

申请日：2007-03-15

Applicant: Adrien R. Lavoie ,  Mark Doczy

Inventor： Adrien R. Lavoie ,  Mark Doczy

IPC: H01L29/00 ,  H01L21/44

CPC classification number: H01L21/28061 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the reactor be less than or equal to 150° C., introducing methylpyrrolidine:alane (MPA) proximate to the surface of the barrier layer, and carrying out a CVD process to deposit aluminum metal on the barrier layer using a bottom-up deposition mechanism.

Abstract translation: 用于执行替换金属栅极工艺的方法包括在反应器中提供晶体管，其中晶体管包括栅极堆叠，去除栅极堆叠的至少一部分以暴露阻挡层的表面，引起反应器的温度 小于或等于150℃，在阻挡层的表面附近引入甲基吡咯烷：甲烷（MPA），并且进行CVD工艺以使用自底向上沉积机理将铝金属沉积在阻挡层上。

公开(公告)号：US20080090397A1

公开(公告)日：2008-04-17

申请号：US11986510

申请日：2007-11-21

Applicant: Justin Brask ,  Brian Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

Inventor： Justin Brask ,  Brian Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC: H01L21/3205

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract translation: 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US20080087985A1

公开(公告)日：2008-04-17

申请号：US11998236

申请日：2007-11-29

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

IPC: H01L23/58

CPC classification number: H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract translation: 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。

公开(公告)号：US20070152271A1

公开(公告)日：2007-07-05

申请号：US11322745

申请日：2005-12-30

Applicant: Gilbert Dewey ,  Mark Doczy ,  Suman Datta ,  Justin Brask ,  Matthew Metz

Inventor： Gilbert Dewey ,  Mark Doczy ,  Suman Datta ,  Justin Brask ,  Matthew Metz

IPC: H01L21/8234 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

Abstract translation: 本文公开了半导体器件和新型半导体器件的制造方法。 示例性的方法包括在执行任何高温处理步骤之前，在栅介质层上原位溅射覆盖层。

公开(公告)号：US20070145468A1

公开(公告)日：2007-06-28

申请号：US11322089

申请日：2005-12-28

Applicant: Amlan Majumdar ,  Suman Datta ,  Been-Yih Jin ,  Mark Doczy ,  Robert Chau

Inventor： Amlan Majumdar ,  Suman Datta ,  Been-Yih Jin ,  Mark Doczy ,  Robert Chau

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/66825

Abstract: Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.

Abstract translation: 本发明的一些实施例包括与非易失性存储晶体管相关的装置和方法。

公开(公告)号：US07198820B2

公开(公告)日：2007-04-03

申请号：US10642426

申请日：2003-08-15

Applicant: Kari Härkönen ,  Mark Doczy ,  Teemu Lang ,  Nathan E. Baxter

Inventor： Kari Härkönen ,  Mark Doczy ,  Teemu Lang ,  Nathan E. Baxter

IPC: C23C16/32

CPC classification number: C23C16/32 ,  C23C16/45527 ,  C23C16/45531 ,  C23C16/4554 ,  Y10T428/12625

Abstract: A process depositing a carbon- and transition metal-containing thin film on a substrate involves placing a substrate within a reaction space and sequentially pulsing into the reaction space a transition metal chemical and an organometallic chemical. Following each chemical pulse, the reaction space is purged, and the pulse and purge sequence is repeated until a desired film thickness is obtained. A preferred deposition process uses atomic layer deposition techniques and may result in an electrically conductive thin carbide film having uniform thickness over a large substrate area and excellent adhesion and step coverage properties.

Abstract translation: 将含碳和过渡金属的薄膜沉积在衬底上的工艺包括将衬底放置在反应空间内，并顺序地将过渡金属化学品和有机金属化学物质脉冲入反应空间。 在每个化学脉冲之后，清除反应空间，重复脉冲和吹扫顺序，直到获得所需的膜厚度。 优选的沉积工艺使用原子层沉积技术，并且可以导致在大的衬底区域上具有均匀厚度的导电薄膜碳化物膜和优异的粘附性和阶梯覆盖性。

公开(公告)号：US20070069293A1

公开(公告)日：2007-03-29

申请号：US11238444

申请日：2005-09-28

Applicant: Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Uday Shah ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Uday Shah ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823828 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Abstract translation: 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可以在连续的宽度范围内定义。

公开(公告)号：US07192856B2

公开(公告)日：2007-03-20

申请号：US11037860

申请日：2005-01-18

Applicant: Mark Doczy ,  Lawrence D. Wong ,  Valery M. Dubin ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Mark Doczy ,  Lawrence D. Wong ,  Valery M. Dubin ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Abstract translation: 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 可以使用催化金属通过表面活化来填充沟槽，然后通过化学沉积种子层，然后从底部向上填充超融合填充物。

公开(公告)号：US20070040227A1

公开(公告)日：2007-02-22

申请号：US11586791

申请日：2006-10-26

Applicant: Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

Inventor： Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/4983 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可能暴露于还原反应的垂直部分。 作为还原反应的结果，垂直部分可以转化为金属，这增加了现有的栅电极。 在一些实施例中，在一些实施例中，去除垂直电介质部分减少了边缘电容，并且还可以有利地稍微增加向下扩散而不加热。