公开(公告)号：US06483176B2

公开(公告)日：2002-11-19

申请号：US09740881

申请日：2000-12-21

申请人： Mitsuhiro Noguchi ,  Akira Nishiyama

发明人： Mitsuhiro Noguchi ,  Akira Nishiyama

IPC分类号： H01L23495

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical wiring structure capable of improving a wiring delay to thereby achieve both low power consumption and high-speed performances without accompanying any significant changes in circuit layout and wiring structure of prior known CMOS logic circuitry and also alterations of the multilayer configuration of wiring layers is provided. A local wiring 1 and global wirings 2, 3 are stacked over a semiconductor substrate 10 in this order of sequence when looked at from lower part in a lamination direction, with dielectric layers sandwiched between adjacent ones of these layers. A distance between the local wiring 1 and the global wiring 2 is so formed as to be greater than a distance between the global wiring layer 2 and the global wiring 3. Thus provided is a semiconductor device featured in that a drive voltage used to drive the global wirings 2, 3 is potentially lower than a drive voltage for driving inside of the local wiring 1.

摘要翻译： 一种能够改善布线延迟从而实现低功耗和高速性能的电布线结构，而不伴随现有已知CMOS逻辑电路的电路布局和布线结构的任何显着变化以及布线层的多层配置的改变。 提供。 当从层叠方向的下部观察时，局部布线1和全局布线2,3以顺序的顺序堆叠在半导体衬底10上，其中介电层夹在这些层中的相邻层之间。 局部布线1和全局布线2之间的距离被形成为大于全局布线层2和全局布线3之间的距离。因此，提供了一种半导体器件，其特征在于用于驱动 全局布线2,3可能低于用于驱动本地布线1内部的驱动电压。

公开(公告)号：US06313511B1

公开(公告)日：2001-11-06

申请号：US09537111

申请日：2000-03-29

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： H01L2976

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： An electrical circuit for measuring threshold voltages and also a circuit for controlling threshold value variations, while avoiding a need to significantly modify or alter the circuit layout, are provided. A semiconductor device has a plurality of substrate conductor regions commonly shared by multiple metal insulator semiconductor field effect transistors (MISFETs) of the same conductivity type, wherein each of the plurality of substrate conductor regions is electrically separated or isolated from one another.

摘要翻译： 提供了用于测量阈值电压的电路以及用于控制阈值变化的电路，同时避免了显着修改或改变电路布局的需要。 半导体器件具有由相同导电类型的多个金属绝缘体半导体场效应晶体管（MISFET）共同共享的多个基板导体区域，其中多个基板导体区域中的每一个彼此电隔离或隔离。

公开(公告)号：US06268629B1

公开(公告)日：2001-07-31

申请号：US09455159

申请日：1999-12-06

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： H01L2976

CPC分类号： H01L21/76232 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/66537

摘要： In a field effect transistor, an element isolation trench is formed around the element region on the major surface of a silicon substrate. A gate electrode is formed on the major surface in the element region via a gate insulating film. Source and drain regions are formed on the major surface of the element region to oppose via a channel region under the gate electrode. The channel region has a main portion having an upper surface at a level higher than the upper end portion of a trench side wall, and a side portion having an upper surface tilting downward from the main portion to the upper end portion of the trench side wall. The dopant impurity in the channel region has a concentration peak located at a level lower than the upper end portion of the trench side wall. The distance from the upper surface of the main portion to the concentration peak is larger than that from the upper surface of the side portion to the peak.

摘要翻译： 在场效应晶体管中，在硅衬底的主表面上的元件区域周围形成元件隔离沟槽。 栅极通过栅极绝缘膜形成在元件区域的主表面上。 源极和漏极区域形成在元件区域的主表面上，以经由栅电极下面的沟道区域相对。 沟道区具有主表面高于沟槽侧壁的上端部的上表面，并且具有从沟槽侧壁的主要部分到上端部向下倾斜的上表面的侧部 。 沟道区域中的掺杂剂杂质具有位于比沟槽侧壁的上端部低的水平的浓度峰。 从主要部分的上表面到浓度峰的距离大于从侧部的上表面到峰的距离。

公开(公告)号：US5804851A

公开(公告)日：1998-09-08

申请号：US820626

申请日：1997-03-19

申请人： Mitsuhiro Noguchi ,  Masami Aoki

发明人： Mitsuhiro Noguchi ,  Masami Aoki

IPC分类号： H01L21/76 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/108 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/945

摘要： A semiconductor memory device comprises a semiconductor substrate having a plurality of trenches selectively formed thereon, a plurality of capacitors formed in the trenches, each of the capacitors formed of the substrate, a capacitor insulating film formed on a surface of each of the trenches, and a storage node buried in each of the trenches interposing the capacitor insulating film, a plurality of transistors, formed on the substrate, for forming memory cells in relation to the plurality of capacitors, each of the transistors having a gate electrode formed on the substrate interposing a gate insulating film and source and drain regions formed in the substrate on both sides of the gate electrode, a plurality of element isolation films formed on side surfaces of upper portions of the trenches to surround the circumference thereof, respectively, the element isolation films having adjacent ones of the isolation films selectively coupled to each other such that at least one of the transistors is electrically insulated from another one of the transistors, and a plurality of conductive members, each connecting one of the source and drain regions of each of the transistors to the storage node of a corresponding one of the capacitors.

摘要翻译： 半导体存储器件包括：半导体衬底，其具有选择性地形成在其上的多个沟槽，形成在沟槽中的多个电容器，由衬底形成的每个电容器，形成在每个沟槽的表面上的电容器绝缘膜，以及 埋置在插入电容器绝缘膜的每个沟槽中的存储节点，形成在衬底上的多个晶体管，用于形成与多个电容器相关的存储单元，每个晶体管具有形成在衬底上的栅电极 栅极绝缘膜和形成在栅电极两侧的基板中的源极和漏极区域，分别形成在沟槽的上部的侧表面以围绕其周边的多个元件隔离膜，元件隔离膜具有 相邻的隔离膜选择性地彼此耦合，使得至少一个隔离膜 每个晶体管与另一个晶体管电绝缘，以及多个导电构件，每个导体构件将每个晶体管的源极和漏极区域中的一个连接到相应的一个电容器的存储节点。

公开(公告)号：US08884353B2

公开(公告)日：2014-11-11

申请号：US13092662

申请日：2011-04-22

申请人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US08625349B2

公开(公告)日：2014-01-07

申请号：US12618200

申请日：2009-11-13

申请人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Mitsuhiro Noguchi ,  Kikuko Sugimae ,  Masato Endo ,  Takuya Futatsuyama ,  Koji Kato ,  Kanae Uchida

发明人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Mitsuhiro Noguchi ,  Kikuko Sugimae ,  Masato Endo ,  Takuya Futatsuyama ,  Koji Kato ,  Kanae Uchida

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  H01L27/11521 ,  H01L27/11526

摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.

摘要翻译： 存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线 第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。 控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向 第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

公开(公告)号：US08546909B2

公开(公告)日：2013-10-01

申请号：US13234644

申请日：2011-09-16

申请人： Mitsuhiko Noda ,  Hiroyuki Kutsukake ,  Mitsuhiro Noguchi

发明人： Mitsuhiko Noda ,  Hiroyuki Kutsukake ,  Mitsuhiro Noguchi

IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L29/792 ,  H01L23/58 ,  H01L21/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/42324

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括元件区域，栅极绝缘膜，第一栅极电极，栅极间绝缘膜，第二栅极电极和元件隔离区域。 栅极绝缘膜形成在元件区域上。 第一栅电极形成在栅极绝缘膜上。 栅极绝缘膜形成在第一栅电极上并具有开口。 第二栅电极形成在栅间绝缘膜上并经由开口与第一栅电极接触。 元件隔离区域包围由元件区域，栅极绝缘膜和第一栅极电极形成的层叠结构。 在元件隔离区域和元件区域，栅极绝缘膜和第一栅极电极的侧表面之间形成气隙。

公开(公告)号：US20130187208A1

公开(公告)日：2013-07-25

申请号：US13713341

申请日：2012-12-13

申请人： Aya Minemura ,  Kenji Sawamura ,  Mitsuhiro Noguchi

发明人： Aya Minemura ,  Kenji Sawamura ,  Mitsuhiro Noguchi

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/76232

摘要： According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.

摘要翻译： 根据一个实施例，半导体器件包括沿着第一方向延伸的有源区域，位于有源区域的第一部分上的接触插塞和位于与有源区域中的有源区域的第一部分相邻的第二部分的晶体管 第一个方向 第一部分的垂直于第一方向的第二方向的顶表面积的宽度小于第二部分在第二方向上的顶表面积的宽度。

公开(公告)号：US08476138B2

公开(公告)日：2013-07-02

申请号：US13150768

申请日：2011-06-01

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L21/8239

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

公开(公告)号：US20120236619A1

公开(公告)日：2012-09-20

申请号：US13231510

申请日：2011-09-13

申请人： Hiroyuki KUTSUKAKE ,  Kikuko SUGIMAE ,  Mitsuhiro NOGUCHI

发明人： Hiroyuki KUTSUKAKE ,  Kikuko SUGIMAE ,  Mitsuhiro NOGUCHI

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11519 ,  H01L27/11529

摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列和外围电路。 存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。 外围电路具有晶体管组。 晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。 第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。 关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。