公开(公告)号：US20040165071A1

公开(公告)日：2004-08-26

申请号：US10654972

申请日：2003-09-05

申请人： NEC ELECTRONICS CORPORATION

发明人： Shinji Kashiwagi

IPC分类号： H04N005/225

CPC分类号： G01R31/318555 ,  G01R31/318541

摘要： A boundary-scan device to a macro is disclosed. A plurality of signal paths are connected to the macro, each having a data signal input end and a data signal output end for signal transmission during normal mode operations. A plurality of circuitries are provided for the plurality of signal paths, respectively. Each circuitry has capability of capturing a signal transmission event that a signal has past through one of the plurality of signal paths during test mode operations.

摘要翻译： 公开了一种到宏的边界扫描装置。 多个信号路径连接到宏，每个具有数据信号输入端和用于正常模式操作期间的信号传输的数据信号输出端。 分别为多个信号路径提供多个电路。 每个电路具有在测试模式操作期间捕获信号已经经过多个信号路径之一的信号传输事件的能力。

公开(公告)号：US20040160834A1

公开(公告)日：2004-08-19

申请号：US10645585

申请日：2003-08-22

申请人： NEC ELECTRONICS CORPORATION

发明人： Yasushi Aoki

IPC分类号： G11C007/00

CPC分类号： G11C27/02

摘要： A latch circuit includes a sample section for responding to complementary clock signals to sample complementary data signals during a sample period, a latch section for latching the sampled complementary data signals on latch output nodes to transfer the same through latch output nodes during a hold period, and a precharge section for precharging the latch output nodes during the sample period. The latch circuit has a smaller dead zone including a smaller setup time and a smaller hold time.

摘要翻译： 锁存电路包括用于响应互补时钟信号以在采样周期期间采样互补数据信号的采样部分，用于在锁存输出节点处锁存采样的互补数据信号的锁存部分，以在保持周期期间将其传送到锁存输出节点， 以及用于在采样周期期间对锁存输出节点进行预充电的预充电部分。 锁存电路具有较小的死区，包括较小的建立时间和较小的保持时间。

公开(公告)号：US20040160269A1

公开(公告)日：2004-08-19

申请号：US10775194

申请日：2004-02-11

申请人： NEC CORPORATION ,  NEC ELECTRONICS CORPORATION

发明人： Hiroshi Tsuchi

IPC分类号： G06G007/12

CPC分类号： G09G3/3685 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0252 ,  G09G2330/02 ,  G09G2330/021

摘要： A driving circuit that drives a capacitive load to a target voltage within a power supply voltage range, includes: a first amplifier circuit having a first operating range, for charging and driving an output terminal and a second amplifier circuit having a second operating range, for discharging and driving the output terminal, and an input control circuit for supplying one of a voltage at an upper limit side (V1) of a range common to the first and second operating ranges, a voltage at a lower limit side (V2) of the range, and a target voltage (Vin) to an input terminal of the first or second amplifier circuit are provided. A driving period for driving the output terminal to the target voltage includes a first period (T1) during which the input control circuit supplies the voltage (V1) or the voltage (V2) to the input terminals of the first and second amplifier circuits and a second period (T2) for supplying the target voltage (Vin) to the input terminals of the first and second amplifier circuits.

摘要翻译： 一种将电容性负载驱动到电源电压范围内的目标电压的驱动电路，包括：具有第一工作范围的第一放大器电路，用于对输出端子进行充电和驱动，以及具有第二工作范围的第二放大器电路， 放电和驱动输出端子;以及输入控制电路，用于提供在第一和第二操作范围共同的范围的上限侧（V1）处的电压中的一个，在下限侧的电压（V2） 并且提供到第一或第二放大器电路的输入端的目标电压（Vin）。 用于将输出端子驱动到目标电压的驱动周期包括输入控制电路向第一和第二放大器电路的输入端提供电压（V1）或电压（V2）的第一周期（T1）和 用于将目标电压（Vin）提供给第一和第二放大器电路的输入端的第二周期（T2）。

公开(公告)号：US20040159896A1

公开(公告)日：2004-08-19

申请号：US10781001

申请日：2004-02-18

申请人： NEC Electronics Corporation

发明人： Takao Honda

IPC分类号： H01L029/76

CPC分类号： G06F1/12 ,  H03K5/1506

摘要： To provide a semiconductor integrated circuit device that reduces charging and discharging currents flowing through clock tree synthesis, thereby reducing current consumption of entire circuits of the semiconductor integrated circuit device. In a semiconductor integrated circuit device including a clock synchronous type circuit that operates in synchronization with either of rising and falling edges flank of a reference clock and a plurality of clock buffer circuits for distributing the reference clock to the clock synchronous type circuit, each clock buffer circuit is constituted from a first transistor that drives a load at one of the edges flank of the reference clock with which the clock synchronous type circuit does not operate in synchronization and a second transistor that drives the load at the other edge flank of the reference clock. A gate width of the first transistor is set so that a change in the edge flank is slowed down, provided that a pulse waveform of the reference clock is not destroyed. A carrier type of the second transistor is different from the carrier type of the first transistor, and the second transistor is formed to have the gate width larger than the first transistor.

摘要翻译： 提供一种降低通过时钟树合成流动的充电和放电电流的半导体集成电路器件，从而降低半导体集成电路器件的整个电路的电流消耗。 在包括与参考时钟侧面的上升沿和下降沿同步操作的时钟同步型电路和用于将参考时钟分配给时钟同步型电路的多个时钟缓冲电路的半导体集成电路器件中，每个时钟缓冲器 电路由第一晶体管构成，该第一晶体管驱动时钟同步型电路不同步操作的参考时钟侧面的一侧边缘处的负载，以及驱动参考时钟的另一边缘处的负载的第二晶体管 。 设置第一晶体管的栅极宽度，使得边缘侧面的变化减慢，只要参考时钟的脉冲波形不被破坏。 第二晶体管的载体类型与第一晶体管的载流子类型不同，并且第二晶体管形成为具有大于第一晶体管的栅极宽度。

公开(公告)号：US20040155316A1

公开(公告)日：2004-08-12

申请号：US10774463

申请日：2004-02-10

申请人： NEC ELECTRONICS CORPORATION

发明人： Yumi Saito ,  Hiroshi Tsuda

IPC分类号： H01L029/00

CPC分类号： H01L22/34 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor reliability evaluating apparatus for evaluating an electro-migration characteristic of a wiring layer which is capable of being formed simply and in a low cost using a reticle set, having a minimum number of reticles, which is capable of measuring an ordinary via plug resistance where the number of wiring layer is two. A first wiring layer and a second wiring layer are configured so that the first wiring layer is connected to the second wiring layer with a plurality of via plugs formed in an insulating layer which is placed between the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are made of metals having almost same specific resistances, and each different parasitic resistances are put to at least one of the first wiring layer and the second wiring layer connected to each of the plurality of via plugs to make the total resistance value of the current path through each of the plurality of via plugs different.

摘要翻译： 提供一种半导体可靠性评估装置，其用于评估能够简单且低成本地使用具有最小数量的标线集的简单且成本低的能够测量普通通孔的布线层的电迁移特性 插头电阻，其中布线层数为2。 第一布线层和第二布线层被构造成使得第一布线层与形成在布置在第一布线层和第二布线层之间的绝缘层中的多个通孔相连接到第二布线层， 第一布线层和第二布线层由具有几乎相同电阻的金属制成，并且将不同的寄生电阻放置在与多个通孔插头中的每一个连接的第一布线层和第二布线层中的至少一个上， 通过每个多个通孔插头的电流路径的总电阻值不同。

公开(公告)号：US20040150112A1

公开(公告)日：2004-08-05

申请号：US10761204

申请日：2004-01-22

申请人： NEC ELECTRONICS CORPORATION

发明人： Noriaki Oda

IPC分类号： H01L023/48 ,  H01L029/40

CPC分类号： H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/85205 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.

摘要翻译： 在半导体衬底上具有接合焊盘的半导体器件包括：上铜层，其形成在接合焊盘的下表面上，插入有阻挡金属，并且其铜面积比大于形成电路互连的层的铜面积比 ; 以及与上部铜层电绝缘且比上部铜层更靠近半导体基板的下部铜层。

公开(公告)号：US20040150070A1

公开(公告)日：2004-08-05

申请号：US10649771

申请日：2003-08-28

申请人： NEC Electronics Corporation

发明人： Norio Okada ,  Hirokazu Aizawa ,  Hiroyasu Minda

IPC分类号： H01L029/00

CPC分类号： H01L23/564 ,  H01L22/32 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： In a provided semiconductor device, a plurality of seal rings each made of a conductive material is formed along a periphery of the semiconductor chip and as to surround the circuit formation portion, the seal rings being connected with the semiconductor substrate and being buried in the plurality of wiring insulating films in such a manner as to extend over the wiring insulating films, and one or more slit-like notches are formed at specified positions in the plurality of seal rings in such a manner that the respective slit-like notches in two seal rings being adjacent to each other are not aligned.

摘要翻译： 在所提供的半导体器件中，沿着半导体芯片的周边形成由导电材料制成的多个密封环，并且为了包围电路形成部分，密封环与半导体衬底连接并被埋在多个 以布线绝缘膜的方式延伸布线绝缘膜，并且在多个密封环中的特定位置处形成一个或多个狭缝状凹口，使得两个密封件中的各个狭缝状凹口 彼此相邻的环不对齐。

公开(公告)号：US20040132299A1

公开(公告)日：2004-07-08

申请号：US10738043

申请日：2003-12-18

申请人： NEC ELECTRONICS CORPORATION

发明人： Motoaki Matsuda ,  Masahiro Ibe

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： H01L21/4846 ,  C25D3/60 ,  C25D5/18 ,  H01L21/4821 ,  H05K3/3473

摘要： In accordance with the present invention, there is provided a method for depositing a lead-free tin alloy on a substrate. The substrate includes an external lead portion of a semiconductor device. The substrate is contacted with an electrolyte composition for depositing the lead-free tin alloy. Current is cyclically passed in a first direction through the electrolyte composition during ON-duty cycle portions to deposit the lead-free tin alloy on the substrate. The passing of current in the first direction through the electrolyte composition is cyclically prevented during OFF-duty cycle portions.

摘要翻译： 根据本发明，提供了一种在基板上沉积无铅锡合金的方法。 衬底包括半导体器件的外部引线部分。 使基板与用于沉积无铅锡合金的电解质组合物接触。 在ON-占空比部分期间，电流在第一方向上循环通过电解质组合物，以将无铅锡合金沉积在基底上。 在OFF占空比部分期间循环地防止沿着第一方向通过电解质组合物的电流。

公开(公告)号：US20040129964A1

公开(公告)日：2004-07-08

申请号：US10740439

申请日：2003-12-22

申请人： NEC ELECTRONICS CORPORATION

发明人： Takashi Nakagawa

IPC分类号： H01L027/108

CPC分类号： H01L28/56 ,  H01L21/31691

摘要： This invention provides a semiconductor memory device having a capacitor which comprises a ferroelectric layer with the perovskite crystal structure which, being expressed by the general formula ABO3, contains lead (Pb) as the element A occupying lattice A and zirconium (Zr) and titanium (Ti) as the element B occupying lattice B, and a lower electrode and an upper electrode which are disposed to sandwich said ferroelectric layer; wherein said ferroelectric layer has, both on the side of said lower electrode and on the side of said upper electrode, a region each, in which a ratio of Zr to Ti (a Zr/Ti ratio) is equal to or greater than a Zr/Ti ratio of the central section of said ferroelectric layer in the direction of thickness, and the Zr/Ti ratio of at least one of the regions on the side of said lower electrode and on the side of said upper electrode is greater than the Zr/Ti ratio of said central section.

摘要翻译： 本发明提供一种具有电容器的半导体存储器件，该电容器包括具有钙钛矿型晶体结构的铁电体层，其以通式ABO3表示，含有作为构成晶格A的元素A的铅（Pb）和锆（Zr）和钛（ Ti）作为元素B占据晶格B，下电极和上电极被设置成夹着所述铁电层; 其中所述铁电层在所述下电极的侧面和所述上电极的侧面上都具有Zr与Ti的比率（Zr / Ti比）等于或大于Zr的区域 所述强电介质层的中心部分的厚度方向的Ti / Ti比，所述下部电极侧和所述上部电极侧的至少一个区域的Zr / Ti比大于Zr / Ti比。

公开(公告)号：US20040123249A1

公开(公告)日：2004-06-24

申请号：US10623575

申请日：2003-07-22

申请人： NEC Electronics Corporation

发明人： Koichi Sato ,  Hiroshi Shibuya ,  Hitoshi Kurosaka

IPC分类号： G06F017/50

CPC分类号： G06F17/5022

摘要： An apparatus for estimating power consumption includes an behavioral synthesizing unit and a clock-based simulation unit. The behavioral synthesizing unit is provided with an algorithm-level description as an input and converts the algorithm-level description to a clock-based description and behavioral synthesis information. The clock-based description and behavioral synthesis information are input to the clock-based simulation unit, which proceeds to execute a clock-based simulation and calculates a power consumption factor of a storage element based upon both the clock-based description and behavioral synthesis information.

摘要翻译： 用于估计功耗的装置包括行为合成单元和基于时钟的模拟单元。 行为合成单元具有作为输入的算法级描述，并将算法级描述转换为基于时钟的描述和行为综合信息。 基于时钟的描述和行为综合信息被输入到基于时钟的仿真单元，该单元继续执行基于时钟的仿真，并且基于基于时钟的描述和行为综合信息来计算存储元件的功耗因数 。