公开(公告)号：US20110027959A1

公开(公告)日：2011-02-03

申请号：US12898421

申请日：2010-10-05

Applicant: Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

Inventor： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC: H01L21/336

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract translation: 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US20100308379A1

公开(公告)日：2010-12-09

申请号：US12477757

申请日：2009-06-03

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

Abstract translation: 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

公开(公告)号：US07737532B2

公开(公告)日：2010-06-15

申请号：US11220176

申请日：2005-09-06

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

Abstract translation: 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 表示包括{l，m，n}的米勒指数族，其中l2 + m2 + n2> i2 + j2 + k2。 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

公开(公告)号：US07592619B2

公开(公告)日：2009-09-22

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L29/15

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US07582934B2

公开(公告)日：2009-09-01

申请号：US12040877

申请日：2008-03-01

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L27/12

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

公开(公告)号：US20090096750A1

公开(公告)日：2009-04-16

申请号：US11871164

申请日：2007-10-12

Applicant: Wen-Chin LEE

Inventor： Wen-Chin LEE

IPC: G06F3/033

CPC classification number: G06F3/03543 ,  G06F3/0362

Abstract: The major characteristic of the present invention lies in the adoption of electromagnetic means to translate the spin of a wheel module into continuous electrical signals. A permanent magnet is incorporated in the wheel module to provide magnetic field. Two sensors tangential to the spinning direction of the permanent magnet are used to detect the variations of the magnetic field from the spin of the wheel module in accordance with the Hall Effect.

Abstract translation: 本发明的主要特征在于采用电磁装置将车轮模块的旋转转换为连续的电信号。 永磁体被并入车轮模块中以提供磁场。 与永磁体的旋转方向相切的两个传感器用于根据霍尔效应来检测来自车轮模块的旋转的磁场的变化。

公开(公告)号：US07511348B2

公开(公告)日：2009-03-31

申请号：US11717450

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7845

Abstract: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

Abstract translation: 第一和第二CMOS晶体管的通道可以选择性地受到压力。 第一晶体管的栅极结构包括在第一晶体管的沟道中产生应力的应力源。 第二晶体管的栅极结构设置成与在第二晶体管的沟道中产生应力的材料层接触。

公开(公告)号：US20090050354A1

公开(公告)日：2009-02-26

申请号：US12057654

申请日：2008-03-28

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H05K1/03

CPC classification number: H05K1/056 ,  H05K1/0393 ,  H05K2201/0355 ,  H05K2201/0382

Abstract: A printed circuit board substrate includes an insulation matrix and a waterproof layer. The insulation matrix includes a first surface and a second surface at an opposite side thereof to the first surface. The waterproof layer is formed in the insulation matrix and is arranged between the first surface and the second surface for blocking water from passing therethrough in a thicknesswise direction of the insulation matrix.

Abstract translation: 印刷电路板基板包括绝缘基体和防水层。 绝缘矩阵包括与第一表面相对的第一表面和第二表面。 防水层形成在绝缘基体中，并且布置在第一表面和第二表面之间，用于阻挡水在绝缘基体的厚度方向上穿过其中。

公开(公告)号：US07466008B2

公开(公告)日：2008-12-16

申请号：US11717484

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L27/06 ,  H01L27/07

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

Abstract translation: 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20080264675A1

公开(公告)日：2008-10-30

申请号：US11847297

申请日：2007-08-29

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H05K1/00 ,  B23K26/38

CPC classification number: H05K3/281 ,  B23K1/0016 ,  B23K26/361 ,  H05K3/0035 ,  H05K3/28 ,  H05K3/3452

Abstract: An exemplary method for manufacturing a printed circuit board is provided. In the method, firstly, a circuit substrate having a substrate and a number of soldering pads is provided. Secondly, a protective layer is formed onto the circuit substrate in a manner such that the soldering pads are entirely covered by the protective layer. Fourthly, a laser beam is applied onto portions of the protective layer spatially corresponding to the soldering pads in a manner such that the portions of the protective layer is removed, thereby exposing the soldering pads to an exterior. A printed circuit board having a protective layer with high precision of resolution is also provided.

Abstract translation: 提供了制造印刷电路板的示例性方法。 在该方法中，首先，提供具有基板和多个焊盘的电路基板。 其次，以使得焊盘完全被保护层覆盖的方式在电路基板上形成保护层。 第四，以保护层的部分被去除的方式将激光束施加到空间对应于焊盘的保护层的部分上，从而将焊盘暴露于外部。 还提供了具有高精度分辨率的保护层的印刷电路板。