公开(公告)号：US06989296B2

公开(公告)日：2006-01-24

申请号：US10844877

申请日：2004-05-12

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L21/44

CPC分类号： H01L23/055 ,  H01L21/50 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/05599 ,  H01L2924/00

摘要： A fabrication method of a semiconductor package with a photosensitive chip is provided. A substrate having a core is prepared. An interposer is mounted on the substrate, with a peripheral portion of the substrate exposed from the interposer. A molding process is performed and the substrate is clamped between an upper mold and a lower mold, with the interposer received in an upwardly-recessed cavity of the upper mold. A molding compound is injected into the upwardly-recessed cavity to form a dam on the peripheral portion of the substrate. Then the upper and lower molds and the interposer are removed from the substrate to expose area covered by the interposer on the substrate. At least one photosensitive chip is mounted on the exposed area of the substrate. A lid seals the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

摘要翻译： 提供了具有感光芯片的半导体封装的制造方法。 制备具有芯的衬底。 插入器安装在衬底上，衬底的周边部分从插入件露出。 进行成型工艺，并且将基板夹在上模具和下模具之间，其中插入件容纳在上模具的向上凹入的空腔中。 将模塑料注入到上凹腔中以在基材的周边部分上形成坝。 然后将上模和下模和插入件从基板上移除以露出基板上由插入件覆盖的区域。 至少一个感光芯片安装在基板的暴露区域上。 盖子密封大坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。

公开(公告)号：US20050194667A1

公开(公告)日：2005-09-08

申请号：US11112108

申请日：2005-04-21

申请人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US20050194665A1

公开(公告)日：2005-09-08

申请号：US11112106

申请日：2005-04-21

申请人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20050184368A1

公开(公告)日：2005-08-25

申请号：US11112109

申请日：2005-04-21

申请人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US06884652B2

公开(公告)日：2005-04-26

申请号：US10420427

申请日：2003-04-22

申请人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/48 ,  H01L21/68 ,  H01L23/31 ,  H01L21/44 ,  H01L21/50

CPC分类号： H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US06847104B2

公开(公告)日：2005-01-25

申请号：US10377545

申请日：2003-02-27

申请人： Chien Ping Huang ,  Chih-Ming Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan

发明人： Chien Ping Huang ,  Chih-Ming Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC分类号： H01L23/16 ,  H01L23/31 ,  H01L23/495 ,  H01L23/02

CPC分类号： H01L23/16 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A window-type ball grid array (WBGA) semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame has a plurality of leads encompassing an opening, each lead having an upper surface and an opposing lower surface. A resin material is pre-molded on the lower surfaces of the leads, with wire-bonding portions and ball-implanting portions defined on the leads being exposed. At least a chip is mounted on the upper surfaces of the leads and covers the opening, allowing the chip to be electrically connected to the wire-bonding portions of the leads by a plurality of bonding wires via the opening. Then, an encapsulant is formed to encapsulate the chip and fill into the opening for encapsulating the bonding wires. Finally, solder balls are implanted on the ball-implanting portions of the leads to complete fabrication of the semiconductor package.

摘要翻译： 提供了一种具有引线框架作为芯片载体的窗型球栅阵列（WBGA）半导体封装及其制造方法。 引线框架具有包围开口的多个引线，每个引线具有上表面和相对的下表面。 在引线的下表面上预先模塑树脂材料，其中限定在引线上的引线接合部分和球注入部分被暴露。 至少芯片安装在引线的上表面上并覆盖开口，允许芯片通过多个接合线通过开口与引线的引线接合部分电连接。 然后，形成密封剂以封装芯片并填充到用于封装接合线的开口中。 最后，将焊球注入到引线的球注入部分上以完成半导体封装的制造。

公开(公告)号：US06828665B2

公开(公告)日：2004-12-07

申请号：US10319262

申请日：2002-12-13

申请人： Han-Ping Pu ,  Chih-Ming Huang ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chih-Ming Huang ,  Chien-Ping Huang

IPC分类号： H01L2302

CPC分类号： H01L23/5385 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/141 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/0401

摘要： A module device of stacked semiconductor packages and a method for fabricating the module device are proposed, wherein a first semiconductor package provided, and at least a second semiconductor package is stacked on and electrically connected to the first semiconductor package. The first semiconductor package includes a chip carrier for mounting at least a chip thereon; a circuit board positioned above and electrically connected to the chip carrier by a plurality of conductive elements; and an encapsulant for encapsulating the chip, conductive elements and encapsulant with a top surface of the circuit board being exposed, allowing the second semiconductor package to be electrically connected to the exposed top surface of the circuit board. As the circuit board is incorporated in the first semiconductor package by means of the encapsulant, it provides preferably reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package.

公开(公告)号：USD492314S1

公开(公告)日：2004-06-29

申请号：US29192300

申请日：2003-10-21

申请人： Chih-Ming Huang ,  Chien-Ping Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan ,  Cheng-Hsu Hsiao

设计人： Chih-Ming Huang ,  Chien-Ping Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan ,  Cheng-Hsu Hsiao

公开(公告)号：US06380082B2

公开(公告)日：2002-04-30

申请号：US09250631

申请日：1999-02-16

申请人： Chih-Ming Huang ,  Tsu-An Lin

发明人： Chih-Ming Huang ,  Tsu-An Lin

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/76808 ,  H01L21/76843

摘要： An improved method of preventing copper poisoning in the fabrication of metal interconnects on a semiconductor substrate comprises sequential formation of a copper layer, a first stop layer, a first inter-metal dielectric layer, a second stop layer, and a second inter-metal dielectric layer over the substrate. The second inter-metal dielectric layer and the second stop layer are defined to form an opening. A conformal first glue/barrier layer is formed over the substrate. The first glue/barrier layer and the first inter-metal dielectric layer are patterned to form a via hole below the opening until the first stop layer is exposed. Spacers are formed on sidewalls of the opening and the via hole below the opening. The first stop layer at bottom of the via hole is removed to expose the copper layer.

摘要翻译： 在半导体衬底的金属互连制造中防止铜中毒的改进方法包括顺序地形成铜层，第一阻挡层，第一金属间介电层，第二阻挡层和第二金属间电介质 层。 第二金属间介电层和第二阻挡层被限定为形成开口。 在衬底上形成共形的第一胶/阻挡层。 将第一胶/阻挡层和第一金属间介电层图案化以在开口下方形成通孔，直到暴露第一​​停止层。 间隔件形成在开口的侧壁和开口下方的通孔中。 去除通孔底部的第一停止层以露出铜层。

公开(公告)号：US08367926B2

公开(公告)日：2013-02-05

申请号：US12944654

申请日：2010-11-11

申请人： Wen-Tang Peng ,  Chih-Ming Huang

发明人： Wen-Tang Peng ,  Chih-Ming Huang

IPC分类号： H01B3/16 ,  H01J5/00 ,  H02G3/14 ,  H01R13/44 ,  H02B5/00

CPC分类号： H01R13/5213 ,  H01R2201/06

摘要： An electronic apparatus includes an enclosure defining a connector port, and a cover mechanism. The cover mechanism includes a bracket mounted to the enclosure, a cover rotatably mounted to the bracket to cover or uncover the connector port. The cover includes an elastic lock. When the cover is rotated to cover the connector port, the elastic lock is engaged with a sidewall of the connector port.

摘要翻译： 电子设备包括限定连接器端口的外壳和盖机构。 盖机构包括安装到外壳的支架，可旋转地安装到支架以覆盖或露出连接器端口的盖。 盖子包括弹性锁。 当盖旋转以覆盖连接器端口时，弹性锁与连接器端口的侧壁接合。