公开(公告)号：US08159878B2

公开(公告)日：2012-04-17

申请号：US12915706

申请日：2010-10-29

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L29/788

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，所述鳍结构包括具有第一导电类型的浮置衬底区域，其被配置为将数据存储为易失性存储器; 第一和第二区域与浮动衬底区域相接合，第一和第二区域中的每一个具有第二导电类型; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。

公开(公告)号：US08159868B2

公开(公告)日：2012-04-17

申请号：US12545623

申请日：2009-08-21

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C11/00

CPC分类号： G11C14/0045 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G11C11/14 ,  G11C11/404 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2211/5643 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/24 ,  H01L27/2445 ,  H01L27/2463 ,  H01L29/7841 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

摘要翻译： 提供半导体存储器，其中存储单元包括具有浮动体的无电容器晶体管，其被配置为当向单元施加电力时将数据作为电荷存储在其中。 电池还包括非易失性存储器，其包括电阻变化元件，电阻变化元件被配置为在多个预定条件中的任何一个下存储存储在浮动体中的数据。 描述了一种操作半导体存储器以用作易失性存储器的方法，同时当功率停止到半导体存储器时具有保留存储数据的能力。

公开(公告)号：US08130548B2

公开(公告)日：2012-03-06

申请号：US12797320

申请日：2010-06-09

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00

CPC分类号： G11C11/404 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L29/7841 ,  H01L29/7881

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

公开(公告)号：US20120014188A1

公开(公告)日：2012-01-19

申请号：US13244855

申请日：2011-09-26

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C7/10 ,  G11C11/402 ,  G11C7/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7395 ,  H01L29/7455 ,  H01L29/7841 ,  H01L29/7881

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

摘要翻译： 提供了保持存储器单元的状态而不中断对存储单元的访问的方法，包括向单元施加反向偏置以将电荷泄漏偏离电池的浮动体，其中浮体的充电水平指示 记忆单元的状态; 并访问该单元格。

公开(公告)号：US20120014180A1

公开(公告)日：2012-01-19

申请号：US13246582

申请日：2011-09-27

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储装置包括多个存储单元，每个存储单元具有用于存储，读取和写入数据作为易失性存储器的浮动体。 该装置包括用于将数据存储为非易失性存储器的浮动栅极或捕获层，该装置在向该装置施加电力时作为易失性存储器工作，并且该装置将来自易失性存储器的数据作为非易失性存储器， 设备中断

公开(公告)号：US20120012915A1

公开(公告)日：2012-01-19

申请号：US13244839

申请日：2011-09-26

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： H01L29/788

CPC分类号： G11C11/404 ,  G11C11/56 ,  G11C11/565 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

摘要翻译： 半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于所述第一和第二区域之间的门; 以及背偏置区域，被配置为将电荷注入或从所述浮体区域中提取电荷以维持存储单元的所述状态。 将背偏置施加到背偏置区域将电荷泄漏偏离浮体，并对电池执行保持操作。 单元可以是多级单元。 公开了用于制造存储器件的存储器单元阵列。

公开(公告)号：US20110032756A1

公开(公告)日：2011-02-10

申请号：US12897528

申请日：2010-10-04

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34

CPC分类号： H01L27/10802 ,  G11C11/34 ,  G11C11/404 ,  G11C11/409 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/7841 ,  H01L29/7881

摘要： An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

摘要翻译： 一种包括半导体存储单元的链路或串的集成电路，其中每个存储单元包括用于存储数据的浮动体区域。 所述链接或连接包括至少一个被配置为将存储器单元电连接到至少一个控制线的触点，并且串或链接中的触点数量与串或链接中的存储器单元的数量相同或小于 。

公开(公告)号：US20100246277A1

公开(公告)日：2010-09-30

申请号：US12797334

申请日：2010-06-09

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7395 ,  H01L29/7455 ,  H01L29/7841 ,  H01L29/7881

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

摘要翻译： 提供了保持存储器单元的状态而不中断对存储单元的访问的方法，包括向单元施加反向偏置以将电荷泄漏偏离电池的浮动体，其中浮体的充电水平指示 记忆单元的状态; 并访问该单元格。

公开(公告)号：US20100034041A1

公开(公告)日：2010-02-11

申请号：US12533661

申请日：2009-07-31

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C11/34

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2211/4016 ,  H01L29/7841

摘要： Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

公开(公告)号：US20090108322A1

公开(公告)日：2009-04-30

申请号：US12256868

申请日：2008-10-23

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L29/00

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，所述鳍结构包括具有第一导电类型的浮置衬底区域，其被配置为将数据存储为易失性存储器; 第一和第二区域与浮动衬底区域相接合，第一和第二区域中的每一个具有第二导电类型; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。