公开(公告)号：US20200052106A1

公开(公告)日：2020-02-13

申请号：US16101162

申请日：2018-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Neal Makela ,  Pei Liu ,  Jiehui Shu ,  Chih-chiang Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28

Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.

公开(公告)号：US10559686B2

公开(公告)日：2020-02-11

申请号：US16018970

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Hui Zang ,  Steven R. Soss

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08

Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.

公开(公告)号：US10546775B1

公开(公告)日：2020-01-28

申请号：US16052085

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US10529724B2

公开(公告)日：2020-01-07

申请号：US16056660

申请日：2018-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Kwan-Yong Lim

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20190341468A1

公开(公告)日：2019-11-07

申请号：US15971043

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/28

Abstract: A method includes forming a semiconductor device including a plurality of fins formed above a substrate, an isolation structure positioned between the plurality of fins, a plurality of sacrificial gate structures defining gate cavities, and a first dielectric material positioned between the sacrificial gate structures. A gate cut structure is formed in a first gate cavity. A trim etch process is performed to reduce a width of the gate cut structure. Replacement gate structures are formed in the gate cavities after performing the trim etch process. A first replacement gate structure in the first gate cavity is segmented by the gate cut structure.

公开(公告)号：US20190341448A1

公开(公告)日：2019-11-07

申请号：US15968968

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie M.S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.

公开(公告)号：US10461155B2

公开(公告)日：2019-10-29

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US10439026B2

公开(公告)日：2019-10-08

申请号：US15786284

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu Wong ,  Hui Zang ,  Xusheng Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

公开(公告)号：US20190295898A1

公开(公告)日：2019-09-26

申请号：US16403745

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311

Abstract: Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.