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    Forming fins of different materials on the same substrate
    91.
    发明授权
    Forming fins of different materials on the same substrate 有权
    在同一基板上形成不同材料的翅片

    公开(公告)号：US09368492B2

    公开(公告)日：2016-06-14

    申请号：US14054009

    申请日：2013-10-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

    IPC: H01L21/82 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/02123 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7856

    Abstract: A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.

    Abstract translation: 半导体衬底可以通过提供一种提供绝缘体上半导体（SOI）衬底而形成，该衬底包括基底半导体层，在该半导体基底上方的掩埋绝缘体层，以及包含掩埋绝缘体层之上的第一半导体材料的SOI层 ; 在所述SOI层中形成隔离区，其将所述SOI层的第一部分与所述SOI层的第二部分隔离; 去除所述SOI层的所述第二部分以暴露所述掩埋绝缘体层的一部分; 在所述掩埋绝缘体层的暴露部分中形成孔以暴露所述基底半导体层的一部分; 以及在所述基底半导体层的所述暴露部分上形成由第二半导体材料制成的半导体层，使得所述替换半导体层覆盖所述掩埋绝缘体层的所述暴露区域。

    Multi-height FinFETs with coplanar topography background
    94.
    发明授权
    Multi-height FinFETs with coplanar topography background 有权
    具有共面形貌背景的多高度FinFET

    公开(公告)号：US09331201B2

    公开(公告)日：2016-05-03

    申请号：US13906428

    申请日：2013-05-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795

    Abstract: A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other.

    Abstract translation: 提供半导体结构，其半导体鳍片具有可变的高度，而没有任何不适当的形貌。 半导体结构包括具有第一半导体表面和第二半导体表面的半导体衬底，其中第一半导体表面垂直偏移并位于第二半导体表面上方。 氧化物区域直接位于第一半导体表面和/或第二半导体表面上。 具有第一高度的第一组第一半导体散热片位于半导体衬底的第一半导体表面之上。 具有第二高度的第二组第二半导体翅片位于第二半导体表面上方，其中第二高度不同于第一高度，并且其中每个第一半导体鳍片和每个第二半导体鳍片具有彼此共面的最顶面。

    FINFET SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
    95.
    发明申请
    FINFET SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES 有权
    FINFET半导体器件与替代门结构

    公开(公告)号：US20160093692A1

    公开(公告)日：2016-03-31

    申请号：US14962015

    申请日：2015-12-08

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: A device includes first and second fins defined in a semiconductor substrate and a raised isolation post structure positioned between the first and second fins, wherein an upper surface of the raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface of each of the first and second fins. A first space is defined by a sidewall of the first fin and a first sidewall of the raised isolation post structure, a second space is defined by a sidewall of the second fin and a second sidewall of the raised isolation post structure, and a gate structure is positioned around a portion of each of the first and second fins and around a portion of the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces.

    Abstract translation: 一种装置包括限定在半导体衬底中的第一和第二鳍片和位于第一鳍片和第二鳍片之间的凸起隔离柱结构，其中凸起隔离柱结构的上表面处于大致等于或大于水平面的水平面 对应于第一和第二鳍片中的每一个的上表面。 第一空间由第一鳍片的侧壁和凸起隔离柱结构的第一侧壁限定，第二空间由第二鳍片的侧壁和凸起隔离柱结构的第二侧壁限定，以及栅极结构 围绕所述第一和第二鳍片中的每一个的一部分并且围绕所述凸起隔离柱结构的一部分定位，其中所述栅极结构的至少部分位于所述第一和第二空间中。

    FinFET semiconductor device with a recessed liner that defines a fin height of the FinFet device
    97.
    发明授权
    FinFET semiconductor device with a recessed liner that defines a fin height of the FinFet device 有权
    FinFET半导体器件具有限定FinFet器件鳍片高度的凹陷衬垫

    公开(公告)号：US09269815B2

    公开(公告)日：2016-02-23

    申请号：US14333135

    申请日：2014-07-16

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

    Abstract translation: 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

    Stacked semiconductor device
    99.
    发明授权
    Stacked semiconductor device 有权
    堆叠半导体器件

    公开(公告)号：US09224811B2

    公开(公告)日：2015-12-29

    申请号：US14215398

    申请日：2014-03-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

    IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/15

    CPC classification number: H01L29/0673 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/155 ,  H01L29/42392 ,  H01L29/78696

    Abstract: A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.

    Abstract translation: 堆叠的半导体器件包括第一对垂直堆叠的自对准纳米线，第二对垂直堆叠的自对准纳米线和半导体衬底上的栅极，第一对垂直堆叠的自对准纳米线的栅极周围部分 和第二对垂直堆叠的自对准纳米线。 第一外延可以合并第一对垂直堆叠的自对准纳米线，并且第二外延可以合并第二对垂直堆叠的自对准纳米线。 层叠的半导体器件可以通过在半导体衬底上形成晶格鳍并围绕晶格鳍的一部分形成栅极来制造。 垂直堆叠的自对准纳米线可以通过从晶格鳍选择性地去除多个层来形成。

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