公开(公告)号：US11830787B2

公开(公告)日：2023-11-28

申请号：US16532956

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/38 ,  H01L25/18 ,  H01L23/00 ,  H03H9/205 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/427 ,  H03H9/05 ,  H03H9/02 ,  H01L23/498 ,  H10N10/17 ,  H10N30/88 ,  H10N39/00 ,  H01L23/552

CPC classification number: H01L23/38 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/18 ,  H03H9/02102 ,  H03H9/0514 ,  H03H9/205 ,  H10N10/17 ,  H10N30/883 ,  H10N39/00 ,  H01L23/552 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2223/6644 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/3025 ,  H01L2924/30111

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US20230198058A1

公开(公告)日：2023-06-22

申请号：US17556784

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Telesphor Kamgaing ,  Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Brandon Rawlings

IPC: H01M50/117 ,  H01L23/58

CPC classification number: H01M50/117 ,  H01L23/58

Abstract: Embedded batteries within glass cores are disclosed. Example apparatus include a glass core layer having opposing first and second surfaces, the glass core layer including a cavity extending from the first surface toward the second surface, and a battery including a first conductive material positioned in the cavity, a second conductive material positioned in the cavity, and an electrolyte to separate the first conductive material from the second conductive material.

公开(公告)号：US20230187371A1

公开(公告)日：2023-06-15

申请号：US17550457

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Rachael J. Parker ,  David Johnston ,  Georgios Dogiamis

IPC: H01L23/544 ,  H01L23/498 ,  H04L9/32

CPC classification number: H01L23/544 ,  H01L23/49838 ,  H04L9/3278 ,  H01L2223/54413

Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first level, each one of the first plurality of IC dies having respective first physical unclonable function (PUF) circuits; a second IC die having a second PUF circuit and a security circuit; a second plurality of IC dies in a second level, the second level not coplanar with the first level, the first level and the second level being coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects; and conductive pathways between the first plurality of IC dies and the second IC die for communication between the first PUF circuits and the second PUF circuit, the conductive pathways comprising a portion of the interconnects.

公开(公告)号：US20230178513A1

公开(公告)日：2023-06-08

申请号：US17543419

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Georgios Dogiamis ,  Bradley A. Jackson ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/50 ,  H01L24/80 ,  H01L24/96 ,  H01L24/16 ,  H01L2225/06572 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.

公开(公告)号：US20220416393A1

公开(公告)日：2022-12-29

申请号：US17359138

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Johanna Swan ,  Adel Elsherbini ,  Shawna Liff ,  Beomseok Choi ,  Qiang Yu

IPC: H01P3/16 ,  H01L25/065 ,  H01P1/208 ,  H01L23/538 ,  H01P5/107 ,  H01L23/66

Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

公开(公告)号：US20220173489A1

公开(公告)日：2022-06-02

申请号：US17672876

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan

IPC: H01P3/16 ,  H01L23/66 ,  H01P11/00

Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

公开(公告)号：US20210408656A1

公开(公告)日：2021-12-30

申请号：US16912027

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC: H01P3/16

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US20210407903A1

公开(公告)日：2021-12-30

申请号：US16914062

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Henning Braunisch ,  Beomseok Choi ,  William J. Lambert ,  Stephen Morein ,  Ahmed Abou-Alfotouh ,  Johanna Swan

IPC: H01L23/522 ,  H01L23/532 ,  H05K1/11 ,  H05K3/14 ,  H01L21/768

Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

公开(公告)号：US20210407888A1

公开(公告)日：2021-12-30

申请号：US16914066

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Stephen Morein ,  Feras Eid ,  Georgios Dogiamis

IPC: H01L23/467 ,  B01F13/00 ,  C23C24/04 ,  H01L23/473

Abstract: A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.

公开(公告)号：US20210398715A1

公开(公告)日：2021-12-23

申请号：US16909264

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Johanna Swan ,  Georgios Dogiamis

IPC: H01B13/00 ,  H01B13/22 ,  H01L21/768 ,  H01B7/00 ,  H01B7/18

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.