公开(公告)号：US12033953B2

公开(公告)日：2024-07-09

申请号：US16830853

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3025

Abstract: A substrate may be included in an electronic device. The substrate may include a first layer that may include a dielectric material. The first layer may define a substrate surface. The substrate may include a second layer optionally including the dielectric material. The second layer may be coupled to the first layer. A wiring trace may be located in the substrate. A recess may extend through the substrate surface, the first layer, and may extend through the second layer. A substrate interconnect may be located within the recess. The substrate interconnect may be at least partially located below the substrate surface. The substrate interconnect may be in electrical communication with the wiring trace.

公开(公告)号：US11929295B2

公开(公告)日：2024-03-12

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L23/3121 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/82 ,  H01L2924/01029 ,  H01L2924/1811

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20230409084A1

公开(公告)日：2023-12-21

申请号：US18458919

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Chee Chun Yee ,  David W. Browning ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Howe Yin Loo ,  Poh Tat Oh

IPC: G06F1/16 ,  G06F3/041

CPC classification number: G06F1/1652 ,  G06F1/1641 ,  G06F1/1643 ,  G06F1/1626 ,  G06F1/1675 ,  G06F3/041 ,  G06F2203/04102

Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.

公开(公告)号：US20230091395A1

公开(公告)日：2023-03-23

申请号：US17483670

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Mooi Ling Chang ,  Poh Boon Khoo ,  Chu Aun Lim ,  Min Suet Lim ,  Prabhat Ranjan

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.

公开(公告)号：US11586473B2

公开(公告)日：2023-02-21

申请号：US17317679

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

IPC: G06F9/50 ,  G06N3/08 ,  G06N3/04 ,  G06F11/30 ,  G06K9/62

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

公开(公告)号：US11445608B2

公开(公告)日：2022-09-13

申请号：US16903845

申请日：2020-06-17

Applicant: Intel Corporation

Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

IPC: H05K1/14 ,  H01R12/61 ,  H05K1/11

Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

公开(公告)号：US20220186716A1

公开(公告)日：2022-06-16

申请号：US17561605

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Mark J. Gallina ,  Min Suet Lim ,  Jianfang Zhu

IPC: F03G7/06 ,  H02N10/00

Abstract: Particular embodiments described herein provide for a flexible vapor chamber with shape memory material for an electronic device. In an example, the electronic device can include a flexible vapor chamber and shape memory material coupled to the shape memory material. When the shape memory material is activated, the shape memory material moves a portion of the flexible vapor chamber to a position that helps with heat dissipation of heat collected by the flexible vapor chamber.

公开(公告)号：US20210100101A1

公开(公告)日：2021-04-01

申请号：US16903845

申请日：2020-06-17

Applicant: Intel Corporation

Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

IPC: H05K1/14 ,  H05K1/11 ,  H01R12/61

Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

公开(公告)号：US10943864B2

公开(公告)日：2021-03-09

申请号：US16469100

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  J-Wing Teh ,  Bok Eng Cheah

IPC: H01L23/525 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L27/02

Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

公开(公告)号：US20210035738A1

公开(公告)日：2021-02-04

申请号：US16306889

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01G4/224 ,  H05K1/02 ,  H01G4/005 ,  H01L23/16 ,  H05K3/28 ,  H01L49/02

Abstract: Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.