公开(公告)号：US20180277433A1

公开(公告)日：2018-09-27

申请号：US15909462

申请日：2018-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Su Chen Fan ,  Huai Huang ,  Koichi Motoyama ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76843 ,  H01L23/53257 ,  H01L23/53266

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

公开(公告)号：US20180083117A1

公开(公告)日：2018-03-22

申请号：US15826346

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Johnathan E. Faltermeier ,  Su Chen Fan ,  Sivananda K. Kanakasabapathy ,  Injo Ok ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/845 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

公开(公告)号：US09735054B2

公开(公告)日：2017-08-15

申请号：US15175776

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/027 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09728456B2

公开(公告)日：2017-08-08

申请号：US15420467

申请日：2017-01-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, Jr.

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

公开(公告)号：US20170170070A1

公开(公告)日：2017-06-15

申请号：US15443523

申请日：2017-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09627257B2

公开(公告)日：2017-04-18

申请号：US15175835

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L29/66 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170077098A1

公开(公告)日：2017-03-16

申请号：US15361794

申请日：2016-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Sivananda K. Kanakasabapathy ,  Injo Ok ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

Abstract translation: 提供了一种用于多电压阈值晶体管结构的技术。 窄通道和长通道形成在翅片上。 在翅片上形成外延层，在外延层上形成层间电介质层。 翅片上的垫片定义了窄通道和长通道。 高k电介质材料沉积在窄通道和长沟道中。 在窄沟道和长沟道中的高k电介质材料上沉积金属层。 窄通道中的高k介电材料的高度凹进。 金属层从窄的和长的通道去除。 工作功能金属沉积在窄通道和长通道中。 沉积栅极导电金属以填充窄沟道和长沟道。 覆盖层沉积在结构的顶表面上。

公开(公告)号：US09576901B1

公开(公告)日：2017-02-21

申请号：US15053106

申请日：2016-02-25

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Chih-Chao Yang

IPC: H01L21/44 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53266 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329

Abstract: A method for manufacturing a semiconductor device includes forming a contact area opening in a dielectric structure, depositing a contact area metal in the contact area opening, forming a metal cap layer on the contact area metal, forming one or more dielectric layers on the metal cap layer, forming one or more hard mask layers on the one or more dielectric layers, forming a metallization opening through the one or more dielectric and hard mask layers, wherein the metallization opening exposes the metal cap layer, removing the one or more hard mask layers, and forming a metallization layer in the metallization opening on the metal cap layer.

Abstract translation: 一种制造半导体器件的方法，包括形成在电介质结构中开口的接触区域，在接触区域开口中沉积接触区域金属，在接触区域金属上形成金属覆盖层，在金属帽上形成一个或多个电介质层 在所述一个或多个介电层上形成一个或多个硬掩模层，通过所述一个或多个电介质层和硬掩模层形成金属化开口，其中所述金属化开口暴露所述金属覆盖层，去除所述一个或多个硬掩模层 并且在金属盖层上的金属化开口中形成金属化层。

公开(公告)号：US20170047254A1

公开(公告)日：2017-02-16

申请号：US15175835

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L27/11 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170047252A1

公开(公告)日：2017-02-16

申请号：US15175776

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。