公开(公告)号：US20220246721A1

公开(公告)日：2022-08-04

申请号：US17725471

申请日：2022-04-20

Applicant: INTEL CORPORATION

Inventor： William HSU ,  Biswajeet GUHA ,  Leonard GULER ,  Souvik CHAKRABARTY ,  Jun Sung KANG ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US20220223717A1

公开(公告)日：2022-07-14

申请号：US17703884

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20220199792A1

公开(公告)日：2022-06-23

申请号：US17691926

申请日：2022-03-10

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Mark ARMSTRONG ,  William HSU ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20220131007A1

公开(公告)日：2022-04-28

申请号：US17569643

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Karthik JAMBUNATHAN ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20220093598A1

公开(公告)日：2022-03-24

申请号：US17031832

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20220093589A1

公开(公告)日：2022-03-24

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20210359110A1

公开(公告)日：2021-11-18

申请号：US17390483

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Michael L. HATTENDORF ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

公开(公告)号：US20210305430A1

公开(公告)日：2021-09-30

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Stephen SNYDER ,  Biswajeet GUHA ,  William HSU ,  Urusa ALAAN ,  Tahir GHANI ,  Michael K. HARPER ,  Vivek THIRTHA ,  Shu ZHOU ,  Nitesh KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20210210514A1

公开(公告)日：2021-07-08

申请号：US17187284

申请日：2021-02-26

Applicant: INTEL CORPORATION

Inventor： Martin D. GILES ,  Tahir GHANI

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.