Variable resistance memory devices and methods of manufacturing the same
    93.
    发明授权
    Variable resistance memory devices and methods of manufacturing the same 有权
    可变电阻存储器件及其制造方法

    公开(公告)号:US09373664B2

    公开(公告)日:2016-06-21

    申请号:US14682506

    申请日:2015-04-09

    IPC分类号: H01L29/06 H01L27/24 H01L45/00

    摘要: A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

    摘要翻译: 可变电阻存储器件及其制造方法包括沿第一方向延伸的多个第一导电结构,沿与第一导电结构相交的第一方向的第二方向延伸的多个第二导电结构,第二导电 结构和形成在第一导电结构和第二导电结构彼此重叠的交点处的多个存储单元,并且每个存储单元包括依次堆叠的选择元件和可变电阻元件。 每个第一导电结构的上表面在第二方向上的宽度小于每个选择元件的底表面的宽度。

    NAND flash memory device having dummy memory cells and methods of operating same
    94.
    发明授权
    NAND flash memory device having dummy memory cells and methods of operating same 有权
    具有虚拟存储单元的NAND闪存器件及其操作方法

    公开(公告)号:US08228738B2

    公开(公告)日:2012-07-24

    申请号:US12977419

    申请日:2010-12-23

    IPC分类号: G11C16/04 G11C16/06 G11C16/10

    摘要: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

    摘要翻译: NAND闪速存储器件包括控制电路,其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压,第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个,以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中,控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中,控制电路被配置为在擦除与其串联连接的多个存储器单元时,放弃擦除伪存储器单元。

    3-level non-volatile semiconductor memory device and method of driving the same
    95.
    发明授权
    3-level non-volatile semiconductor memory device and method of driving the same 失效
    3级非易失性半导体存储器件及其驱动方法

    公开(公告)号:US08085607B2

    公开(公告)日:2011-12-27

    申请号:US12830464

    申请日:2010-07-06

    IPC分类号: G11C7/00

    摘要: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

    摘要翻译: 用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关,耦合到第一位线并被配置为传送的第一锁存块 向第一存储器单元提供第一锁存数据,以及耦合到第二位线和第一锁存块的第二锁存块,并且被配置为将第二锁存数据传送到第二存储器单元。

    Multi-bit flash memory devices and methods of programming and erasing the same
    96.
    发明授权
    Multi-bit flash memory devices and methods of programming and erasing the same 有权
    多位闪存设备及其编程和擦除方法

    公开(公告)号:US08072804B2

    公开(公告)日:2011-12-06

    申请号:US12471729

    申请日:2009-05-26

    IPC分类号: G11C11/34

    CPC分类号: G11C11/5628 G11C2211/5641

    摘要: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

    摘要翻译: 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路,其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元,并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS
    98.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS 有权
    用导电模式制作半导体器件的方法

    公开(公告)号:US20110217835A1

    公开(公告)日:2011-09-08

    申请号:US13110113

    申请日:2011-05-18

    IPC分类号: H01L21/28

    摘要: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

    摘要翻译: 公开了一种栅极图案,其包括半导体衬底,下导电图案,上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进,以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

    Non-volatile semiconductor memory devices
    99.
    发明授权
    Non-volatile semiconductor memory devices 有权
    非易失性半导体存储器件

    公开(公告)号:US07968931B2

    公开(公告)日:2011-06-28

    申请号:US12503354

    申请日:2009-07-15

    IPC分类号: H01L29/788

    摘要: A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

    摘要翻译: 非易失性存储器件包括在半导体衬底上的隧道绝缘层,电荷存储层,阻挡绝缘层和栅电极。 电荷存储层位于隧道绝缘层上,并且具有比隧道绝缘层更小的带隙,并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上,并且具有比电荷存储层更大的带隙,并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。

    SEMICONDUCTOR MEMORY DEVICES
    100.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权
    半导体存储器件

    公开(公告)号:US20110095377A1

    公开(公告)日:2011-04-28

    申请号:US12984860

    申请日:2011-01-05

    IPC分类号: H01L27/088

    摘要: In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

    摘要翻译: 在一些实施例中,半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。 半导体存储器件还包括在衬底上的器件隔离图案。 器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。 半导体存储器件还包括第一有源区中的第一公共源极区,多个第一源极/漏极区和第一漏极区。 半导体存储器件还包括第二公共源极区域,多个第二源极/漏极区域和第二有源区域中的第二漏极区域。 半导体存储器件还包括第三有源区中的第三源/漏区。 半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。