公开(公告)号：US06976936B2

公开(公告)日：2005-12-20

申请号：US10829375

申请日：2004-04-22

申请人： Shiro Yamaoka ,  Toshiharu Nogi ,  Atsushi Shimada ,  Nobuyasu Kanekawa ,  Youichi Iihoshi

发明人： Shiro Yamaoka ,  Toshiharu Nogi ,  Atsushi Shimada ,  Nobuyasu Kanekawa ,  Youichi Iihoshi

IPC分类号： F02B11/00 ,  B60K6/20 ,  F02B1/12 ,  F02B13/06 ,  F02D13/02 ,  F02D21/08 ,  F02D29/00 ,  F02D35/02 ,  F02D41/00 ,  F02D41/02 ,  F02D41/04 ,  F02D41/30 ,  F02D41/34 ,  F02D43/00 ,  F02D45/00 ,  F02P5/00 ,  B60K41/04 ,  F02D41/14

CPC分类号： F02D13/0265 ,  B60W10/04 ,  B60W10/10 ,  B60W30/1819 ,  B60W2710/0616 ,  F02B1/12 ,  F02D13/0207 ,  F02D35/023 ,  F02D35/028 ,  F02D41/006 ,  F02D41/008 ,  F02D41/3035 ,  F02D41/3076 ,  F02D2041/001 ,  F02D2041/288 ,  Y02T10/128 ,  Y02T10/18 ,  Y02T10/47 ,  Y02T10/52 ,  Y02T10/84 ,  Y10T477/675 ,  Y10T477/68 ,  Y10T477/688

摘要： In a multi-cylinder engine having a compression ignition combustion mode, a vibration detecting sensor that is preferably mounted in a cylinder block or a cylinder head is used to detect a frequency and the detected frequency is appropriately analyzed to detect or estimate a cylinder pressure peak value and peak timing for each cylinder. An amount of internal EGR, a fuel injection condition, an engine speed and the like are then controlled so as to bring each of these parameters into an appropriate range thereof. The control apparatus suppresses variations in combustion states among different cylinders and different cycles arising from unit-to-unit variations or deterioration in the engine or part-to-part variations or deterioration in a component thereof.

摘要翻译： 在具有压缩点火燃烧模式的多气缸发动机中，优选安装在气缸体或气缸盖中的振动检测传感器用于检测频率，并适当地分析检测到的频率以检测或估计气缸压力峰值 每个气缸的值和峰值定时。 然后控制内部EGR的量，燃料喷射状态，发动机转速等，以使这些参数中的每一个参与其适当的范围。 控制装置抑制由单位变化引起的不同气缸和不同循环之间的燃烧状态的变化，或者发动机的劣化或部件间变化或其部件的劣化。

公开(公告)号：US06344809B1

公开(公告)日：2002-02-05

申请号：US09704687

申请日：2000-11-03

申请人： Nobuyasu Kanekawa ,  Yasuyuki Kojima ,  Seigou Yukutake ,  Minehiro Nemoto ,  Kazuhisa Takami ,  Takayuki Iwasaki ,  Yusuke Takeuchi ,  Yasuo Shima

发明人： Nobuyasu Kanekawa ,  Yasuyuki Kojima ,  Seigou Yukutake ,  Minehiro Nemoto ,  Kazuhisa Takami ,  Takayuki Iwasaki ,  Yusuke Takeuchi ,  Yasuo Shima

IPC分类号： H03M900

CPC分类号： H04L12/10 ,  H04M1/573 ,  H04M3/005

摘要： In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.

摘要翻译： 为了减少隔离器接口和ADC的功率消耗，建议仅在保持电话机的挂机状态的同时从系统交换机提供的电源来操作呼叫信号接收或来电显示信号接收功能。 在正常运行时，模拟数字转换器的输出通过隔离器接口输入到隔离器，在呼叫信号接收或来电识别信息接收时，模拟数字转换器的输出直接输入 到隔离器。

公开(公告)号：US06216236B1

公开(公告)日：2001-04-10

申请号：US09188903

申请日：1998-11-10

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F1134

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。 每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。 三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。 此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

公开(公告)号：US5901281A

公开(公告)日：1999-05-04

申请号：US434288

申请日：1995-05-03

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G11C29/00 ,  G06F11/34

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G06F11/1641 ,  G06F11/18 ,  G06F11/185 ,  G06F11/20 ,  G11C29/74

摘要： A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线连接的多个处理单元。 每个处理单元在公共支撑板（PL）上具有三个或更多个处理器，并由公共时钟单元控制。 三个处理器执行相同的操作，并且通过比较三个处理器的操作来检测处理器中的故障。 如果一个处理器发生故障，则在更换整个处理单元之前，至少暂时在处理单元的其他两个处理器中继续操作。 此外，处理单元可以在时钟单元内具有多个时钟（A，B），具有切换装置，使得处理器通常从主时钟（A）接收时钟脉冲，但是从辅助时钟（B ）如果主时钟（A）失败。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 此外，多个高速缓冲存储器可以共同地连接到处理器，使得一个高速缓冲存储器的故障允许处理单元使用另一高速缓冲存储器继续操作。 可以通过直接比较来实现高速缓冲存储器的内容的一致性，并且还可以使用比较方法来使处理器的内部高速缓冲存储器中的数据与外部高速缓冲存储器中的数据不同。 协议的一致性还可以确保不同处理器单元的高速缓存中的数据总是正确的。

公开(公告)号：US5805797A

公开(公告)日：1998-09-08

申请号：US580336

申请日：1995-12-28

申请人： Hiroshi Sato ,  Nobuyasu Kanekawa ,  Makoto Nohmi ,  Korefumi Tashiro

发明人： Hiroshi Sato ,  Nobuyasu Kanekawa ,  Makoto Nohmi ,  Korefumi Tashiro

IPC分类号： B60L3/08 ,  B61L3/00 ,  B61L3/22 ,  B61L15/00 ,  G05B9/02 ,  G05B9/03 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G08C25/00

CPC分类号： B61L15/0063 ,  B61L25/021 ,  B61L3/008 ,  B61L3/22 ,  G06F11/0796 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1004

摘要： An ATP device generates control data for two systems from an ATP command speed signal, provides duplicate logic units in the ATP device so as to process the respective control data, provides at least two CRC data for checking the control data for each system, and changes the CRC data of the opposite logic unit or selects one of the two according to the content of a failure detection signal from each of the duplicated logic units. It is possible to check the control data and the operation of each logic circuit in such a way that only when all the data, circuits, and elements operate normally will an output signal for controlling the object to be controlled be outputted, and when a failure is detected in a part, an output signal to that effect is outputted. Therefore, when a failure occurs, a fail safe function for performing control on the safe side is made possible.

摘要翻译： ATP设备从ATP命令速度信号生成两个系统的控制数据，在ATP设备中提供重复的逻辑单元，以处理相应的控制数据，提供至少两个用于检查每个系统的控制数据的CRC数据，并且改变 相对逻辑单元的CRC数据或者根据来自每个复制逻辑单元的故障检测信号的内容来选择两者之一。 可以以这样的方式检查每个逻辑电路的控制数据和操作，使得只有当所有的数据，电路和元件正常运行时才能输出用于控制待控制对象的输出信号，并且当故障 在一部分中被检测到，输出这样的输出信号。 因此，当发生故障时，可以进行用于对安全侧执行控制的故障保护功能。

公开(公告)号：US5789805A

公开(公告)日：1998-08-04

申请号：US746942

申请日：1996-11-18

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1/18 ,  G06F3/00 ,  G06F11/10 ,  G06F11/22 ,  G06F12/16 ,  G06F15/78 ,  G11C5/00 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the is surface of the insulating layer, in order to use a portion of the multilayer wing substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层。 优选地，在多层布线基板的表面上部分地形成有绝缘层和形成在绝缘层的表面上的芯片接合接地，以便在芯片接合地下使用多层翼基板的一部分作为 布线或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US5614761A

公开(公告)日：1997-03-25

申请号：US523346

申请日：1995-09-05

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1/18 ,  G06F3/00 ,  G06F11/10 ,  G06F11/22 ,  G06F12/16 ,  G06F15/78 ,  G11C5/00 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层基板。 优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US5612946A

公开(公告)日：1997-03-18

申请号：US493662

申请日：1995-06-22

申请人： Nobuyasu Kanekawa ,  Shoji Suzuki ,  Yoshimichi Sato ,  Shinya Ohtsuji

发明人： Nobuyasu Kanekawa ,  Shoji Suzuki ,  Yoshimichi Sato ,  Shinya Ohtsuji

IPC分类号： G06F11/18 ,  G06F11/00 ,  G06F11/16 ,  H04L12/26

CPC分类号： G06F11/1625 ,  G06F11/1641

摘要： The same electrical device can be used in two modes, a simplex bus connection mode and a duplex bus connection mode, by collating signals output from two input and output ports for two electrical circuits in an electrical device with a comparator and detecting a fault in the electrical circuits in a duplex bus connection mode, and by checking whether a normal signal is output from an input and output port by collating a signal output from one input and output port for one of the two electrical circuits with the output signal fed back via another input and output port in a simplex bus connection mode.

摘要翻译： 通过将具有比较器的电气设备中的两个电路的两个输入和输出端口输出的信号进行整流，可以在两种模式中使用相同的电气设备，即单向总线连接模式和双工总线连接模式，并检测 并且通过将来自两个电路中的一个的一个输入和输出端口输出的信号通过另一个反馈的反馈信号进行核对来检查是否从输入和输出端口输出正常信号 输入和输出端口在单工总线连接模式。

公开(公告)号：US5468992A

公开(公告)日：1995-11-21

申请号：US843234

申请日：1992-02-28

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： G06F1/18 ,  G06F3/00 ,  G06F11/10 ,  G06F11/22 ,  G06F12/16 ,  G06F15/78 ,  G11C5/00 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/28 ,  H01L27/04 ,  H05K3/10

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wire bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer element. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, thereby making it possible to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line being formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line being formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片和布线基板之间形成的引线键合焊盘之间的引线接合来连接。 布线基板可以是多层元件。 优选地，在多层布线基板的表面上形成有绝缘层和形成在绝缘层的表面上的管芯接合接地，从而可以将芯片接合地下的多层布线基板的一部分作为 布线或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线线路优选地包括两条数据总线，与布线基板的一侧上形成的一条数据总线相连的半导体芯片和与另一数据总线相连的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US09146567B2

公开(公告)日：2015-09-29

申请号：US13985627

申请日：2012-02-21

申请人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Ryosuke Ishida

发明人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Ryosuke Ishida

IPC分类号： H02M3/157 ,  G05F1/10 ,  H02P29/02 ,  H02M7/538 ,  H01F7/18 ,  H02M1/32

CPC分类号： G05F1/10 ,  H01F2007/1888 ,  H02M1/32 ,  H02M7/53803 ,  H02P29/0241 ,  H02P29/0243 ,  H02P29/032

摘要： A current control device capable of performing widely applicable failure detection without a motor rotation speed sensor is provided. A current control semiconductor element includes, on a same semiconductor chip, a transistor that drives load, a current detection circuit that detects current of the load, a compensator that calculates an on-duty of the transistor from a current command value and a current value output from the current detection circuit, and a PWM timer that generates a pulse turning on the transistor on the basis of the on-duty. A microcontroller sends the current command value to the current control semiconductor element, receives the current value output from the current detection circuit and the on-duty output from the compensator from the current control semiconductor element, and detects failure of the current control semiconductor element on the basis of the received current value and on-duty.

摘要翻译： 提供一种能够在没有马达转速传感器的情况下执行广泛应用的故障检测的电流控制装置。 电流控制半导体元件在相同的半导体芯片上包括驱动负载的晶体管，检测负载电流的电流检测电路，从电流指令值和电流值计算晶体管的占空比的补偿器 来自电流检测电路的输出;以及PWM定时器，其基于占空比产生导通晶体管的脉冲。 微控制器将电流指令值发送到电流控制半导体元件，从电流控制半导体元件接收从电流检测电路输出的电流值和来自补偿器的占空比输出，并检测电流控制半导体元件的故障 所接受的现值和值班的依据。