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    Method for testing semiconductor components
    91.
    发明授权
    Method for testing semiconductor components 失效
    半导体元件测试方法

    公开(公告)号：US06396291B1

    公开(公告)日：2002-05-28

    申请号：US09723101

    申请日：2000-11-28

    申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    IPC分类号： G01R3102

    CPC分类号： G01R1/0466 ,  G01R1/0483

    摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

    摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

    Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure
    92.
    发明授权
    Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure 失效
    用于测试半导体部件的测试载体，包括用于防止部件挠曲的支撑部件的互连

    公开(公告)号：US06369600B2

    公开(公告)日：2002-04-09

    申请号：US09110231

    申请日：1998-07-06

    申请人： Warren M. Farnworth ,  Mike Hess ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson ,  Salman Akram

    发明人： Warren M. Farnworth ,  Mike Hess ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson ,  Salman Akram

    IPC分类号： G01R3126

    CPC分类号： G01R1/0483 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A test carrier and an interconnect for testing semiconductor components, such as bare dice and chip scale packages, are provided. The carrier includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes interconnect contacts configured to make temporary electrical connections with component contacts (e.g., bond pads, solder balls). The interconnect also includes support members configured to physically contact the component, to prevent flexure of the component due to pressure exerted by the force applying mechanism. The support members can be formed integrally with the interconnect using an etching process. In addition, the support members can include an elastomeric layer to provide cushioning and to accommodate Z-direction dimensional variations.

    摘要翻译： 提供了测试载体和用于测试半导体部件（例如裸芯片和芯片级封装）的互连。 载体包括其上安装有互连件的基座，以及用于将部件抵靠互连件的力施加机构。 互连包括被配置为与部件触点（例如，焊盘，焊球）进行临时电连接的互连触头。 互连还包括被配置为物理地接触部件的支撑部件，以防止部件由于施力机构施加的压力而挠曲。 支撑构件可以使用蚀刻工艺与互连一体地形成。 此外，支撑构件可以包括弹性体层以提供缓冲并适应Z方向尺寸变化。

    Probe card, test method and test system for semiconductor wafers
    93.
    发明授权
    Probe card, test method and test system for semiconductor wafers 失效
    半导体晶圆的探针卡，测试方法和测试系统

    公开(公告)号：US06356098B1

    公开(公告)日：2002-03-12

    申请号：US09394960

    申请日：1999-09-10

    申请人： Salman Akram ,  C. Patrick Doherty ,  Warren M. Farnworth ,  David R. Hembree

    发明人： Salman Akram ,  C. Patrick Doherty ,  Warren M. Farnworth ,  David R. Hembree

    IPC分类号： G01R3126

    CPC分类号： G01R31/2886 ,  G01R1/07378

    摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，测试方法和采用探针卡的测试系统。 探针卡包括：基底; 引脚触点的图案可滑动地安装到基板上; 以及用于使所述销触点偏压以与所述晶片上的芯片触点电接触的施力部件。 在示例性实施例中，施力构件包括与销触点物理和电接触的弹簧加载的电连接器。 或者，施力构件包括用于多个针接触的可压缩垫，或者每个销接触的单独的可压缩垫。 通过选择力施加部件的弹簧力来控制销接触到模具接触部中的穿透深度，并且销的Z方向过驱动量接触到模具接触件中。

    Test system with mechanical alignment for semiconductor chip scale packages and dice
    94.
    发明授权
    Test system with mechanical alignment for semiconductor chip scale packages and dice 失效
    用于半导体芯片级封装和裸片的机械对准测试系统

    公开(公告)号：US06353328B2

    公开(公告)日：2002-03-05

    申请号：US09745093

    申请日：2000-12-20

    申请人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

    发明人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

    IPC分类号： G01R3102

    CPC分类号： G01R1/04 ,  H01L2924/15311

    摘要： A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.

    摘要翻译： 提供了一种用于测试半导体部件的测试系统，例如凸起的芯片和芯片级封装。 测试系统包括用于保持一个或多个部件的基座和用于与部件进行临时电连接的互连。 测试系统还包括具有用于将部件对准互连的对准表面的对准夹具。 另外，组件可以包括对准构件，诸如斜面边缘，凸块或构造成与对准表面相互作用的柱。 对准夹具可以形成为聚合物层，例如抗蚀剂层，其使用晶片级制造工艺沉积，显影，然后固化。 对准表面可以是构造成接合部件边缘的聚合物层中的开口，或者交替地接合对准部件。

    Probe card and testing method for semiconductor wafers
    95.
    发明授权
    Probe card and testing method for semiconductor wafers 有权
    半导体晶圆的探针卡和测试方法

    公开(公告)号：US06275052B1

    公开(公告)日：2001-08-14

    申请号：US09303367

    申请日：1999-04-30

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1073

    CPC分类号： G01R1/073 ,  G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

    Semiconductor package with wire bond protective member
    96.
    发明授权
    Semiconductor package with wire bond protective member 有权
    半导体封装带引线键合保护元件

    公开(公告)号：US06255840B1

    公开(公告)日：2001-07-03

    申请号：US09304941

    申请日：1999-05-04

    申请人： David R. Hembree ,  Salman Akram ,  Derek Gochnour ,  Warren M. Farnworth

    发明人： David R. Hembree ,  Salman Akram ,  Derek Gochnour ,  Warren M. Farnworth

    IPC分类号： G01R3126

    CPC分类号： G01R1/0483 ,  H01L2224/48091 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

    摘要： A package, system and method for testing semiconductor dice are provided. The package include a base for retaining the die, and an interconnect having contact members for establishing temporary electrical connections with the die. Electrical paths are formed between terminal contacts on the base, and the contact members on the interconnect, by wires that are wire bonded to conductors on the base and interconnect. The package includes a protective member for protecting the wires and associated wire bonds during assembly, disassembly and handling of the package. The protective member can be formed as a plate mounted to the base and configured to cover the wires and wire bonds. Alternately the protective member can comprise an encapsulating material such as an epoxy resin or silicone elastomer deposited on the wires and wire bonds and then cured.

    摘要翻译： 提供了一种用于测试半导体晶片的封装，系统和方法。 该封装包括用于保持裸片的基座和具有与模具建立临时电连接的接触构件的互连。 通过引线接合到基座上的导体和互连件上的导线，在基座上的端子触头与互连件上的接触部件之间形成电气路径。 该包装包括用于在组装，拆卸和处理包装过程中保护电线和相关联的线接合的保护构件。 保护构件可以形成为安装到基座并被构造成覆盖电线和引线接合的板。 替代地，保护构件可以包括诸如环氧树脂或硅氧烷弹性体的封装材料，其沉积在电线和引线键上，然后固化。

    Calibration target for calibrating semiconductor wafer test systems
    97.
    发明授权
    Calibration target for calibrating semiconductor wafer test systems 失效
    用于校准半导体晶圆测试系统的校准目标

    公开(公告)号：US06239590B1

    公开(公告)日：2001-05-29

    申请号：US09084732

    申请日：1998-05-26

    申请人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    发明人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    IPC分类号： G01R104

    CPC分类号： G01R35/005 ,  G01R1/073 ,  Y10T29/49197

    摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.

    摘要翻译： 提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。 还提供了使用校准目标的校准方法以及用于制造校准目标的方法。 校准目标包括其上形成有各种三维对准特征的基板。 第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。 对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。 第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。 对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

    Test system with mechanical alignment for semiconductor chip scale packages and dice
    98.
    发明授权
    Test system with mechanical alignment for semiconductor chip scale packages and dice 有权

    公开(公告)号：US06229324B1

    公开(公告)日：2001-05-08

    申请号：US09365461

    申请日：1999-08-02

    申请人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

    发明人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

    IPC分类号： G01R3102

    CPC分类号： G01R1/04 ,  H01L2924/15311

    摘要： A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.