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公开(公告)号:US20190051569A1
公开(公告)日:2019-02-14
申请号:US16162195
申请日:2018-10-16
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Kyle K. Kirby , Luke G. England , Jaspreet S. Gandhi
Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
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92.
公开(公告)号:US20180122762A1
公开(公告)日:2018-05-03
申请号:US15339693
申请日:2016-10-31
Applicant: Micron Technology, Inc.
Inventor: Suresh Yeruva , Kyle K. Kirby , Owen R. Fay , Sameer S. Vadhavkar
Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.
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公开(公告)号:US12272870B2
公开(公告)日:2025-04-08
申请号:US18110872
申请日:2023-02-16
Applicant: Micron Technology, Inc.
Inventor: John F. Kaeding , Owen R. Fay
IPC: H01Q1/48
Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.
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公开(公告)号:US20250046730A1
公开(公告)日:2025-02-06
申请号:US18781737
申请日:2024-07-23
Applicant: Micron Technology, Inc.
Inventor: Andrew M. Bayless , Brandon P. Wirz , Owen R. Fay , Cassie L. Bayless
IPC: H01L23/544 , H01L21/304 , H01L21/3115 , H01L21/32 , H01L23/00
Abstract: Methods, apparatuses, and systems related to a semiconductor structure having an implanted alignment mark. The alignment mark may be formed by implanting a distinguishable material within a thickness of an initial semiconductor wafer and then thinning the initial semiconductor wafer. The distinguishable material may be implanted during, as a part of, or shortly following frontside processing to form active circuitry or portions thereof and then subsequently exposed through the thinning process. The resulting mark may be used to identify a relative location of circuits on the thinned wafer for subsequent processing or bonding.
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公开(公告)号:US12199068B2
公开(公告)日:2025-01-14
申请号:US17817690
申请日:2022-08-05
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Randon K. Richards , Aparna U. Limaye , Dong Soon Lim , Chan H. Yoo , Bret K. Street , Eiichi Nakano , Shijian Luo
IPC: H01L25/065 , H01L21/66 , H01L21/78 , H01L23/00 , H01L23/552 , H01L23/64 , H01L23/66 , H01L25/00 , H01L25/18 , H01Q1/22 , H01Q1/48
Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
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96.
公开(公告)号:US12199001B2
公开(公告)日:2025-01-14
申请号:US18200173
申请日:2023-05-22
Applicant: Micron Technology, Inc.
Inventor: Chan H. Yoo , Owen R. Fay
IPC: H01L23/36 , H01L23/00 , H01L23/42 , H01L23/498 , H01L25/00 , H01L25/065 , H01L25/10 , H05K7/20
Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermal management layer disposed between the first and second devices. The thermal management layer may be configured to reduce heat transfer between the first and second devices.
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97.
公开(公告)号:US20240355783A1
公开(公告)日:2024-10-24
申请号:US18757428
申请日:2024-06-27
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay
IPC: H01L25/065 , H01L21/683 , H01L23/00 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/6835 , H01L23/49838 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/50 , H01L2221/68359 , H01L2224/11462 , H01L2224/11622 , H01L2224/13022 , H01L2224/13109 , H01L2224/16145 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06586 , H01L2924/1431 , H01L2924/1434
Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
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公开(公告)号:US12062607B2
公开(公告)日:2024-08-13
申请号:US17958986
申请日:2022-10-03
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay , Chan H. Yoo
IPC: H01L23/522 , H01L23/31 , H01L23/528 , H01L25/065 , H01M50/414 , H05K9/00
CPC classification number: H01L23/5226 , H01L23/3114 , H01L23/3121 , H01L23/528 , H01L25/0657 , H01M50/414 , H05K9/0083 , H01H2227/014 , H01L2224/80855
Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.
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公开(公告)号:US12051670B2
公开(公告)日:2024-07-30
申请号:US17490224
申请日:2021-09-30
Applicant: Micron Technology, Inc.
Inventor: Mark E. Tuttle , John F. Kaeding , Owen R. Fay , Eiichi Nakano , Shijian Luo
CPC classification number: H01L24/32 , H01L24/29 , H01L24/33 , H01L2224/29078 , H01L2224/32105 , H01L2224/3303 , H01L2224/33107 , H01L2224/3313 , H01L2924/381
Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.
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公开(公告)号:US12027498B2
公开(公告)日:2024-07-02
申请号:US17832019
申请日:2022-06-03
Applicant: Micron Technology, Inc.
Inventor: Owen R. Fay
IPC: H01L25/065 , H01L21/683 , H01L23/00 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/6835 , H01L23/49838 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/50 , H01L2221/68359 , H01L2224/11462 , H01L2224/11622 , H01L2224/13022 , H01L2224/13109 , H01L2224/16145 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06586 , H01L2924/1431 , H01L2924/1434
Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
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