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    MEMORY DEVICE
    91.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20180275885A1

    公开(公告)日：2018-09-27

    申请号：US15465751

    申请日：2017-03-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: G06F3/06 ,  G06F11/16 ,  G06F11/20

    Abstract: A memory device is disclosed. The memory device includes a memory array. The memory array includes a main memory block and an extra memory block. The memory array includes a main bit line and an extra bit line. A ratio of a quantity of the extra memory block to a quantity of the main memory block is a block quantity ratio A. A ratio of a quantity of the extra bit line to a quantity of the main bit line is a bit line quantity ratio B. The block quantity ratio A is larger than the bit line quantity ratio B.

    Memory device comprising memory strings penetrating through a stacking structure and electrically contacting with a metal layer and method for fabricating the same
    93.
    发明授权
    Memory device comprising memory strings penetrating through a stacking structure and electrically contacting with a metal layer and method for fabricating the same 有权
    存储器件包括贯穿堆叠结构并与金属层电接触的存储器串及其制造方法

    公开(公告)号：US09583439B1

    公开(公告)日：2017-02-28

    申请号：US14821874

    申请日：2015-08-10

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L23/528 ,  H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11565

    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a ground layer disposed on the substrate, a stacking structure having a plurality of conductive layers and a plurality of insulating layers alternatively stacked on the ground layer and a plurality of memory strings penetrating through the stacking structure. The ground layer includes a metal layer. The memory strings electrically contact with the metal layer.

    Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，设置在衬底上的接地层，具有多个导电层和交替层叠在接地层上的多个绝缘层的堆叠结构以及贯穿堆叠结构的多个存储器串。 接地层包括金属层。 存储器串与金属层电接触。

    TWISTED ARRAY DESIGN FOR HIGH SPEED VERTICAL CHANNEL 3D NAND MEMORY
    95.
    发明申请
    TWISTED ARRAY DESIGN FOR HIGH SPEED VERTICAL CHANNEL 3D NAND MEMORY 有权
    用于高速垂直通道3D NAND存储器的TWISTED ARRAY设计

    公开(公告)号：US20160268201A1

    公开(公告)日：2016-09-15

    申请号：US15164730

    申请日：2016-05-25

    Applicant: Macronix International Co., Ltd.

    Inventor： Shih-Hung Chen

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/115

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

    Abstract translation: 大体描述，存储器件具有多层导电层。 垂直取向的支柱各自包括在支柱和导电层之间的交叉点处的串联存储单元。 SSL在导电层之上运行，柱和SSL的每个交叉点定义了柱的相应选择门。 位线在SSL之上运行。 柱子布置在相对于位线旋转的规则格栅上。 栅格可以具有正方形，矩形或菱形单元，并且可以相对于位线旋转角度θ，其中tan（θ）=±X / Y，其中X和Y是协整整数。 SSL可以制得足够宽，以便在单元电池的一侧或电池的所有支柱上交叉两个柱，或者足够宽以便在两个或更多个非相邻电池中与柱相交。

    MEMORY REPAIRING METHOD AND MEMORY DEVICE APPLYING THE SAME
    96.
    发明申请
    MEMORY REPAIRING METHOD AND MEMORY DEVICE APPLYING THE SAME 有权
    存储器修复方法和应用该存储器的存储器件

    公开(公告)号：US20160260501A1

    公开(公告)日：2016-09-08

    申请号：US14637476

    申请日：2015-03-04

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: G11C29/44 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00

    CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/76 ,  G11C2029/5604

    Abstract: A memory repairing method and a memory device applying the same are disclosed, wherein the method comprises steps as follows: A memory device comprising at least one page having a plurality of cell strings is firstly provided. A regular data pattern is then provided to block at least two of the plurality of cell strings, and the blocked cells strings are marked as inaccessible.

    Abstract translation: 公开了一种存储器修复方法和应用该存储器修复方法的存储器件，其中该方法包括以下步骤：首先提供包括具有多个单元串的至少一个页面的存储器件。 然后提供常规数据模式以阻止多个单元串中的至少两个，并且被阻止的单元串被标记为不可访问。

    3D NAND memory with decoder and local word line drivers
    97.
    发明授权
    3D NAND memory with decoder and local word line drivers 有权
    具有解码器和本地字线驱动器的3D NAND存储器

    公开(公告)号：US09418743B1

    公开(公告)日：2016-08-16

    申请号：US14623963

    申请日：2015-02-17

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: G11C5/06 ,  G11C16/08

    CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

    Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers. The control circuitry causes the first plurality of conductive lines to select at least a first particular stack in the plurality of stacks, the second plurality of conductive lines to select at least the first particular stack in the plurality of stacks, and the third plurality of conductive lines to select at least one particular layer in the plurality of intermediate layers.

    Abstract translation: 存储器件包括多个导电条的叠层，与多个堆叠正交布置的多个导电垂直结构，在多个堆叠的侧表面之间的交叉点处的界面区域中的存储元件和多个导电垂直结构 ，多个导线和多个控制电路。 导电条的多个叠层与绝缘条交替，包括至少底层的导电条，多个导电条的中间层和导电条的顶层。 第一多个导电线电耦合到导电条的顶层。 电耦合到多个中间层的第二多个导电线和第三多个导电线。 所述控制电路使得所述第一多个导线选择所述多个堆叠中的至少第一特定堆叠，所述第二多个导电线至少选择所述多个堆叠中的所述第一特定堆叠，以及所述第三多个导电 行以选择多个中间层中的至少一个特定层。

    Semiconductor structure
    98.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US09368507B2

    公开(公告)日：2016-06-14

    申请号：US14093072

    申请日：2013-11-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L27/105 ,  H01L27/115 ,  G11C16/04

    CPC classification number: H01L27/11556 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/11578

    Abstract: A semiconductor device comprises a plurality of stacking blocks and a plurality of conductive lines. Each stacking blocks comprises two opposite finger VG structures. Each finger VG structure includes a staircase structure and a plurality of bit line stacks. The staircase structure is perpendicular to the bit line stacks, and the bit line stacks of the two opposite finger VG structures are arranged alternately. The conductive lines is disposed over the stacking blocks at interval. The direction of the conductive lines is parallel to a direction of the bit line stacks. The conductive lines include a plurality of bit lines and a plurality of ground lines, and each stacking block includes at least one ground line.

    Abstract translation: 半导体器件包括多个堆叠块和多个导电线。 每个堆叠块包括两个相对的手指VG结构。 每个手指VG结构包括阶梯结构和多个位线堆叠。 梯形结构垂直于位线堆叠，并且两个相对的手指VG结构的位线堆叠交替布置。 导电线以间隔设置在堆叠块上。 导线的方向平行于位线堆叠的方向。 导线包括多个位线和多个接地线，并且每个堆叠块包括至少一个接地线。

    Parallelogram cell design for high speed vertical channel 3D NAND memory
    100.
    发明授权
    Parallelogram cell design for high speed vertical channel 3D NAND memory 有权
    用于高速垂直通道3D NAND存储器的平行四边形单元设计

    公开(公告)号：US09219073B2

    公开(公告)日：2015-12-22

    申请号：US14582848

    申请日：2014-12-24

    Applicant: Macronix International Co., Ltd.

    Inventor： Shih-Hung Chen

    IPC: H01L27/115 ,  H01L27/02

    CPC classification number: H01L27/11578 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Pillars oriented orthogonally to the substrate each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines (SSLs) are disposed above the conductive layers, and bit lines are disposed above the SSLs. The pillars are arranged on a regular grid having a unit cell which is a non-rectangular parallelogram. The pillars may be arranged so as to define a number of parallel pillar lines, each having an acute angle θ>0° relative to the bit line conductors, each line of pillars having n>1 pillars intersecting a common one of the SSL. The arrangement permits higher bit line density, a higher data rate due to increased parallelism, and a smaller number of SSLs, thereby reducing disturbance, reducing power consumption and reducing unit cell capacitance.

    Abstract translation: 大体描述，存储器件具有多层导电层。 与基板正交取向的支柱各自包括在支柱和导电层之间的交叉点处的串联存储单元。 字符串选择行（SSL）被布置在导电层上方，位线布置在SSL之上。 支柱布置在具有非矩形平行四边形的单元的规则格栅上。 支柱可以布置成限定多个平行的支柱，每条柱线相对于位线导体具有锐角> 0°，每条支柱具有与公共的SSL相交的n> 1个支柱。 该布置允许更高的位线密度，由于增加的并行性而具有较高的数据速率和较少数量的SSL，从而减少干扰，降低功耗并降低单位电池电容。

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