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478 条记录 (耗时 0.029 秒)

    Multimode output stage converting differential to single-ended signals using current-mode input signals
    91.
    发明授权
    Multimode output stage converting differential to single-ended signals using current-mode input signals 有权
    多模输出级使用电流模式输入信号将差分转换为单端信号

    公开(公告)号：US06806771B1

    公开(公告)日：2004-10-19

    申请号：US10159681

    申请日：2002-05-31

    申请人： Paul Hildebrant ,  Jian Li ,  Hans W. Klein

    发明人： Paul Hildebrant ,  Jian Li ,  Hans W. Klein

    IPC分类号： H03G310

    CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2200/261 ,  H03F2200/78 ,  H03F2203/45458 ,  H03F2203/45526 ,  H03G3/001

    摘要： An output block for an in-system programmable analog integrated circuit. The output block features an output amplifier that accepts a differential current-mode input signal and provides a single-ended output voltage. The output amplifier is also selectably operable as a linear amplifier, an integrator or a comparator. The output block also includes a common-mode feedback circuit (CMFB), an analog trim circuit (OATRM), a CLAMP circuit, and an offset calibration circuit (CLDAC), all coupled to the differential input of the output amplifier. The CMFB exhibits bandwidth comparable to that of the output amplifier and a drive capability that enables the differential-input to single-ended output conversion. The CLAMP is connected to the differential input in the comparator mode in order to avoid slow recovery from an overdrive condition. The OATRM forces a difference current into the differential input that compensates for a (gain independent) offset voltage that results from various mismatches. The CLDAC uses a digital-to-analog converter (DAC) to perform offset calibration at the differential input of the output amplifier. In addition, the output block is configured to be operational in a number of user-selectable modes, including, in one embodiment, one or more of: a linear (NORM) mode, a comparator (COMP) mode, and an integrator (INT) mode. An amplifier in the output block is variously reconfigured to achieve the selected mode of operation. Also, the output block accommodates an autocalibration (CAL) technique by clamping the single-ended output stage and balancing, through operation of the CLDAC, signals at an input node and at an interstage node of the amplifier.

    摘要翻译： 用于在系统可编程模拟集成电路的输出块。 输出模块具有输出放大器，可接受差分电流模式输入信号，并提供单端输出电压。 输出放大器也可选择可操作为线性放大器，积分器或比较器。 输出块还包括共模反馈电路（CMFB），模拟微调电路（OATRM），钳位电路和偏移校准电路（CLDAC），全部耦合到输出放大器的差分输入。 CMFB具有与输出放大器的带宽相当的带宽，以及使差分输入能够实现单端输出转换的驱动能力。 CLAMP在比较器模式下连接到差分输入，以避免从过驱动条件恢复缓慢。 OATRM将差分电流强制为差分输入，补偿由各种不匹配产生的（增益无关）偏移电压。 CLDAC使用数模转换器（DAC）在输出放大器的差分输入端执行偏移校准。 此外，输出块被配置为可在多个用户可选模式下操作，包括在一个实施例中，一个或多个：线性（NORM）模式，比较器（COMP）模式和积分器（INT ）模式。 输出块中的放大器被不同地重新配置以实现所选择的操作模式。 此外，输出块通过钳位单端输出级并通过CLDAC的操作在放大器的输入节点和级间节点处的信号进行平衡来适应自动校准（CAL）技术。

    Reliable adhesion layer interface structure for polymer memory electrode and method of making same
    92.
    发明授权
    Reliable adhesion layer interface structure for polymer memory electrode and method of making same 失效
    聚合物记忆电极的可靠粘附层界面结构及其制备方法

    公开(公告)号：US06798003B2

    公开(公告)日：2004-09-28

    申请号：US09909375

    申请日：2001-07-20

    申请人： Jian Li ,  Xiao-Chun Mu

    发明人： Jian Li ,  Xiao-Chun Mu

    IPC分类号： H01L4700

    CPC分类号： H01L27/11507 ,  H01L27/11502 ,  Y10S438/939

    摘要： A polymer memory device includes two organic adhesion layers that facilitate an integral package comprising a lower and an upper electrode and the ferroelectric polymer memory structure. The ferroelectric polymer memory structure includes crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure includes spin-on and/or Langmuir-Blodgett deposited compositions. A memory system allows the polymer memory device to interface with various existing hosts.

    摘要翻译： 聚合物存储器件包括两个有机粘合层，其有助于包含下电极和上电极以及铁电聚合物存储器结构的整体封装。 铁电聚合物记忆结构包括结晶铁电聚合物层，例如单一和共聚物组合物。 该结构包括旋转和/或Langmuir-Blodgett沉积的组合物。存储器系统允许聚合物存储器件与各种现有主机接口。

    Stepped structure for a multi-rank, stacked polymer memory device and method of making same
    95.
    发明授权
    Stepped structure for a multi-rank, stacked polymer memory device and method of making same 失效
    多级堆叠聚合物存储器件的阶梯结构及其制造方法

    公开(公告)号：US06624457B2

    公开(公告)日：2003-09-23

    申请号：US09909670

    申请日：2001-07-20

    申请人： Jian Li ,  Xiao-Chun Mu

    发明人： Jian Li ,  Xiao-Chun Mu

    IPC分类号： H01L31119

    CPC分类号： G11C11/22 ,  B82Y10/00 ,  H01L27/285

    摘要： The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.

    摘要翻译： 铁电聚合物储存装置技术领域本发明涉及一种铁电聚合物储存装置，其包括至少两个层叠的铁电聚合物存储结构，它们被排列在至少两个相应堆叠的拓扑结构之上，该拓扑结构是包括层间电介质层和通孔结构的预制硅衬底腔。

    Self-aligned process for capping copper lines
    98.
    发明授权
    Self-aligned process for capping copper lines 失效
    自动对线加工铜线

    公开(公告)号：US5310602A

    公开(公告)日：1994-05-10

    申请号：US960627

    申请日：1992-10-13

    申请人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    发明人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76858 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/238 ,  Y10T428/239 ,  Y10T428/24917

    摘要： The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.

    摘要翻译： 本发明的特征在于制造铜基多层互连的工艺和所得到的制品。 由本发明的方法形成的基于铜的多层互连首先包括将铜线图案沉积在诸如二氧化硅之类的适用基底上或其中的工艺步骤。 铜线约为1微米厚。 线通过溅射沉积涂覆有约50至100nm的钛，并在氩气氛围中在约300℃至400℃下进行随后的退火。 对钛和铜层进行退火以在铜/钛结处提供Cu 3 Ti合金。 然后通过用氟基蚀刻的干蚀刻剥离铜特征之间的未反应的钛。 剩余的Cu3Ti合金随后在NH3气氛中在大约650℃左右的快速热退火下转化成TiN（O）和铜，然后通常在550℃至650℃的温度范围内 约五分钟。 因此，铜线由TiN（O）层覆盖，因为在热处理期间氧被并入到TiN层中。 作为扩散阻挡层，TiN（O）层比TiN更有效。

    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits
    99.
    发明授权
    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits 失效
    在超大规模集成（ULSI）电路中制造铜互连的工艺

    公开(公告)号：US5277985A

    公开(公告)日：1994-01-11

    申请号：US790971

    申请日：1991-11-12

    申请人： Jian Li ,  Evan Colgan ,  James W. Mayer

    发明人： Jian Li ,  Evan Colgan ,  James W. Mayer

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76867 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/24917

    摘要： The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

    摘要翻译： 本发明在超大规模集成（ULSI）电路的硅衬底上具有低温，自封装的铜互连线。 互连线是包括以下步骤的工艺的产物：（a）将铜与约10原子量的钛的钛合金化; （b）将铜/钛合金层沉积在ULSI电路的二氧化硅/硅衬底上; （c）图案化铜/钛层以在衬底上形成互连线; （d）通过铜/钛互连线以60摄氏度到80摄氏度/分钟的近似斜率的快速加热在铜互连线上形成富钛表面膜; 并且（e）在氨气气氛中在约450至650℃的近似范围内的低温下将互连线的富钛表面渗氮约15至40分钟，以形成围绕所述铜的氮化钛封装层 互连线。