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202 条记录 (耗时 0.058 秒)

    Integrated circuit device fabrication by plasma etching
    91.
    发明授权
    Integrated circuit device fabrication by plasma etching 失效
    通过等离子体蚀刻制造集成电路器件

    公开(公告)号：US5759921A

    公开(公告)日：1998-06-02

    申请号：US531727

    申请日：1995-09-21

    申请人： Michael D. Rostoker

    发明人： Michael D. Rostoker

    IPC分类号： H01L21/3065 ,  H01L21/00

    CPC分类号： H01L21/3065 ,  H01J2237/3347

    摘要： An anisotropic etching process is disclosed in which two sources of process gas are provided to a plasma reactor having at least three electrodes. In a plasma, the first process gas provides etchant species which are reactive with a substrate and the second process gas provides barrier species which protect trench sidewalls from reaction with the etchant species. For etching silicon, the first process gas may be chlorine, chloro-trifluoromethane, oxygen, etc., and the second process gas may be C.sub.2 F.sub.6, SF.sub.6, BCl.sub.3, or other compound that either combines with etchant species on a trench sidewall or forms a protective polymer film on such trench sidewall. A disclosed plasma reactor includes a grounded first electrode which forms part of the reactor's enclosure, a coiled second electrode disposed above and separated from the reactor enclosure by a dielectric shield, and a planar third electrode located below the substrate to be etched. A plasma is generated by providing radio frequency energy from the second electrode to the enclosure interior. The charged species from that plasma are directed to the substrate by applying a bias between the first and third electrodes.

    摘要翻译： 公开了一种各向异性蚀刻工艺，其中将两种工艺气体源提供给具有至少三个电极的等离子体反应器。 在等离子体中，第一工艺气体提供与衬底反应的蚀刻剂物质，并且第二工艺气体提供保护沟槽侧壁不与蚀刻剂物质反应的阻挡物质。 为了蚀刻硅，第一工艺气体可以是氯，氯三氟甲烷，氧等，并且第二工艺气体可以是C2F6，SF6，BCl3或其它化合物，其与沟槽侧壁上的蚀刻剂物质组合或形成 这种沟槽侧壁上的保护性聚合物膜。 所公开的等离子体反应器包括形成反应器外壳的一部分的接地第一电极，设置在反应器外壳上方并通过介电屏蔽分离的线圈第二电极，以及位于待蚀刻基板下方的平面第三电极。 通过从第二电极到外壳内部提供射频能量来产生等离子体。 通过在第一和第三电极之间施加偏压将来自该等离子体的带电物质引导到衬底。

    Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
    92.
    发明授权
    Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures 失效
    用于形成用于集成电路器件的金属互连结构以形成集成电路结构的工艺

    公开(公告)号：US5756395A

    公开(公告)日：1998-05-26

    申请号：US516614

    申请日：1995-08-18

    申请人： Michael D. Rostoker ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Ashok K. Kapoor

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H01L21/283

    CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L23/53242 ,  H01L23/53252 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/0002 ,  Y10S438/975

    摘要： A process for forming an integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure. The one or more layers of metal interconnects are formed on the second substrate by the steps of forming a pattern of metal contacts in the second substrate and level with the surface of the substrate; forming a metal layer over the substrate, preferably of a different metal than the metal contacts; patterning the metal layer to form vias; forming a first layer of dielectric material on the surface of the substrate over the exposed portions of the metal contacts and around the metal vias; forming a further metal layer over the first layer of dielectric material and the metal vias, preferably using a different metal than used for the metal vias; patterning the further metal layer into metal interconnects; and depositing a second layer of dielectric material over the exposed portions of the first layer of dielectric material and around the metal interconnects. In a preferred embodiment, over the uppermost metal layer is formed a layer of low melting alloy material (solder) prior to the step of patterning this metal layer to facilitate the electrical connection of the metal interconnect structure.

    摘要翻译： 描述了一种用于形成集成电路结构的工艺，其中在半导体衬底上和半导体衬底中构成诸如MOS或双极晶体管的各种集成电路器件，并且在第二衬底上并且在第二衬底中构造一个或多个金属互连层，优选地具有类似的厚度 ，然后将两个基板对准并结合在一起，从而提供半导体衬底上的各个集成电路器件与第二衬底上的适当金属互连件的电互连，以提供所需的集成电路结构。 一层或多层金属互连件通过以下步骤形成在第二基板上：在第二基板中形成金属接触图案并与基板的表面平齐; 在衬底上形成金属层，优选地与金属触点不同的金属; 图案化金属层以形成通孔; 在所述金属触点的暴露部分和所述金属通孔周围的所述基板的表面上形成第一介电材料层; 在所述第一介电材料层和所述金属通孔上形成另一金属层，优选使用与用于所述金属通孔不同的金属; 将另外的金属层图案化成金属互连; 以及在所述第一介电材料层的所述暴露部分上并围绕所述金属互连件沉积第二介电材料层。 在优选实施例中，在图案化该金属层的步骤之前，在最上面的金属层上形成低熔点合金材料（焊料）层，以便于金属互连结构的电连接。

    Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method
    94.
    发明授权
    Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method 失效
    集成电路物理设计自动化系统优化处理采用混沌健身改进方法

    公开(公告)号：US5682322A

    公开(公告)日：1997-10-28

    申请号：US229949

    申请日：1994-04-19

    申请人： Douglas B. Boyle ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Michael D. Rostoker

    发明人： Douglas B. Boyle ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Michael D. Rostoker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor .lambda.. The value of .lambda. is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation. This spreads out clumps of cells so that the density of cells is more uniform throughout the placement. The attraction between cells in the nets is balanced against repulsion caused by a high local cell density, providing an optimized tradeoff of wirelength, feasibility and congestion.

    摘要翻译： 通过将至少一些单元重定位到提供较低互连拥塞的新位置来优化用于集成电路芯片的单元布局的适应性。 对于每个单元，计算连接单元的单元格网格的质心。 然后，电池向质心移动一个距离，该距离等于从电池的当前位置到质心乘以“混沌”因子λ的距离。 选择λ的值，使得单元重定位操作将导致放置朝向最佳配置收敛而没有混沌转移，但是具有足够高的混沌元素以防止优化操作变得卡在局部适应度最大值。 可以修改新的单元位置以将单元格的效果包括在其他位置，例如通过将单元密度梯度或力方向的函数合并到计算中。 这扩散了细胞团，使得细胞的密度在整个放置期间更均匀。 网络中的细胞之间的吸引力与由局部细胞密度较高引起的排斥平衡，从而提供了线长，可行性和拥塞的最优化折中。

    Conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structure
    96.
    发明授权
    Conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structure 失效
    具有粗糙表面的导电锗/硅构件适用于集成电路结构

    公开(公告)号：US5644152A

    公开(公告)日：1997-07-01

    申请号：US462653

    申请日：1995-06-05

    申请人： Michael D. Rostoker ,  Ashok Kapoor

    发明人： Michael D. Rostoker ,  Ashok Kapoor

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/161 ,  H01L29/34

    CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L27/11517 ,  H01L29/42324 ,  Y10S148/059

    摘要： A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the toughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

    摘要翻译： 描述了导电构件，其上具有受控粗糙度的表面，其可用于集成电路结构的构造。 在优选实施例中，使用锗和硅的混合物形成导电构件，然后将其氧化，导致在锗/硅导电构件上形成粗糙表面，这是由于锗的氧化速率的差异 和硅。 在氧化导电部件之后，可以去除氧化物层，留下锗/硅导电部件上的增韧表面。 当使用具有粗糙表面的导电部件形成诸如EPROM的集成电路结构时，然后在粗糙表面上沉积另外的氧化物层，随后沉积第二层导电材料，例如多晶硅或锗 /硅混合物，从其形成控制栅极。 然后可以在第二导电层上形成另外的氧化物层，接着形成图案化步骤以分别从第二导电层形成浮栅（来自锗/硅层）和控制栅极。

    Integrated circuit packages with distinctive coloration
    97.
    发明授权
    Integrated circuit packages with distinctive coloration 失效
    具有独特色彩的集成电路封装

    公开(公告)号：US5644102A

    公开(公告)日：1997-07-01

    申请号：US203919

    申请日：1994-03-01

    申请人： Michael D. Rostoker

    发明人： Michael D. Rostoker

    IPC分类号： H01L23/544 ,  H01L23/552 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H05K5/00

    CPC分类号： H01L23/552 ,  H01L23/544 ,  H05K1/0266 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/15162 ,  H01L2924/15312 ,  H05K1/181 ,  H05K2201/09936 ,  H05K2201/10689 ,  H05K2203/161 ,  H05K3/303

    摘要： A technique is described for providing body coloration and colored indicia for indicating one or more characteristics of an integrated circuit device. Package body coloration is one source of information about device characteristics. Other indications relate to colored indicia. The colored indicia are relatively large and easily viewable from distances too great for printed text on the package body to be read comfortably. The indicia is (are) colored other than black or white. Among the visible indicia characteristics which can be used to convey information are: indicia color (or colors on multi-colored indicia), shape, size, orientation, and/or location. Among the various integrated circuit device characteristics which can be conveyed by the indicia characteristics are: device function, device speed, level of testing, degree of rad-hardness, location of reference pin, side, corner or surface, location and function of groups of pins carrying related signals, etc. In order to facilitate assembly, colored indicia matching those on the integrated circuit devices can be printed on a printed circuit board substrate at locations and in orientations on the printed circuit corresponding to the correct assembled positions of the integrated circuit devices. Colored areas can also be incorporated into semiconductor packages to control (alter, modify) the thermal characteristics of the package, particularly in order that thermal stresses on a die operating within the package can be reduced and equalized.

    摘要翻译： 描述了一种用于提供身体着色和彩色标记以指示集成电路器件的一个或多个特性的技术。 包装体颜色是有关设备特性的信息的一个来源。 其他迹象涉及彩色标记。 彩色标记相对较大，从包装体上的打印文本的距离太大可以容易地看到，以便舒适地阅读。 标记是（黑色或白色）以外的颜色。 可用于传达信息的可见标记特征是：标记颜色（或多色标记上的颜色），形状，大小，方向和/或位置。 可以通过标记特性传达的各种集成电路器件特性包括：器件功能，器件速度，测试级别，拉德硬度程度，参考引脚，侧面，拐角或表面的位置，组的位置和功能 带有相关信号的引脚等。为了便于组装，可以将与集成电路器件上的那些相匹配的彩色标记印刷在印刷电路板上的位置和方向上，对应于集成电路的正确组装位置 设备。 彩色区域也可以并入到半导体封装中以控制（改变，修改）封装的热特性，特别是为了减少和均衡在封装内工作的裸片上的热应力。

    Single chip network router
    98.
    发明授权
    Single chip network router 失效
    单芯片网路路由器

    公开(公告)号：US5640399A

    公开(公告)日：1997-06-17

    申请号：US529656

    申请日：1995-09-18

    申请人： Michael D. Rostoker ,  D. Tony Stelliga

    发明人： Michael D. Rostoker ,  D. Tony Stelliga

    IPC分类号： H04L12/46 ,  H04L12/56 ,  H04L12/66 ,  H04L29/06 ,  H04Q11/04 ,  H04J3/14

    CPC分类号： H04Q11/0478 ,  H04L12/4625 ,  H04L12/66 ,  H04L69/22 ,  H04L2012/5615 ,  H04L2012/5616 ,  H04L2012/5652

    摘要： A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

    摘要翻译： 用于复用通信网络的单芯片路由器包括用于存储数据分组的分组存储器，用于在局域网（LAN）协议和广域网（WAN）协议）之间转换分组的简化指令集计算机（RISC）处理器， LAN接口和WAN接口。 直接存储器访问（DMA）控制器在数据包存储器和LAN和WAN接口之间传输数据包传输。 分组属性存储器存储数据分组的属性，并且属性处理器对正被处理的分组的地址执行非线性散列算法，以访问分组属性存储器中的所述分组的相应属性。 地址窗口过滤器通过仅检查所述地址的预定部分来识别正在处理的分组的地址，并且可以包括动态窗口过滤器或静态窗口过滤器。

    Computer implemented method for producing optimized cell placement for integrated circiut chip
    99.
    发明授权
    Computer implemented method for producing optimized cell placement for integrated circiut chip 失效
    用于集成循环芯片生产优化的电池放置的计算机实现方法

    公开(公告)号：US5636125A

    公开(公告)日：1997-06-03

    申请号：US559206

    申请日：1995-11-13

    申请人： Michael D. Rostoker ,  James S. Koford ,  Edwin R. Jones ,  Douglas B. Boyle ,  Ranko Scepanovic

    发明人： Michael D. Rostoker ,  James S. Koford ,  Edwin R. Jones ,  Douglas B. Boyle ,  Ranko Scepanovic

    IPC分类号： G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5072

    摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

    摘要翻译： 在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。 重组优化过程的结果以产生优化的细胞放置。 分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。 该系统可以应用于初始放置，布线，布局改进等问题。 处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。 或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。 处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。