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    Apparatuses and methods for mixed charge pumps with voltage regulator circuits
    91.
    发明授权
    Apparatuses and methods for mixed charge pumps with voltage regulator circuits 有权

    公开(公告)号：US10319417B2

    公开(公告)日：2019-06-11

    申请号：US15815037

    申请日：2017-11-16

    Applicant: Micron Technology, Inc.

    Inventor： Xiaojiang Guo ,  Qiang Tang

    IPC: G11C5/14 ,  G11C16/30 ,  G11C11/4074

    Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.

    Electronic device with a reconfigurable charging mechanism
    93.
    发明授权
    Electronic device with a reconfigurable charging mechanism 有权

    公开(公告)号：US10090759B1

    公开(公告)日：2018-10-02

    申请号：US15693300

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Michele Piccardi ,  Xiaojiang Guo ,  Qiang Tang

    IPC: H02M3/07

    Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.

    Testing impedance adjustment
    94.
    发明授权
    Testing impedance adjustment 有权

    公开(公告)号：US09912498B2

    公开(公告)日：2018-03-06

    申请号：US14639293

    申请日：2015-03-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Qiang Tang ,  Xiaojiang Guo ,  Chang Wan Ha

    IPC: G11C7/00 ,  H04L25/02 ,  G06F13/40 ,  G11C5/04 ,  G11C29/02 ,  G11C29/50

    CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

    Abstract: Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. When no available resistance value of the termination device generates a voltage level at the node that is deemed to match the reference voltage, the voltage level of the reference voltage may be altered, and the voltage level at the node may be compared to the altered reference voltage. When the voltage level at the node is deemed to match the altered reference voltage, the termination device may be deemed as passed. Otherwise, the termination device may be deemed as failed.

    Voltage regulator with current feedback
    98.
    发明授权
    Voltage regulator with current feedback 有权

    公开(公告)号：US09612605B2

    公开(公告)日：2017-04-04

    申请号：US14661706

    申请日：2015-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Ruo-Gu Huang ,  Xiaojiang Guo

    IPC: G05F1/575 ,  G05F3/26

    CPC classification number: G05F3/262

    Abstract: Generally discussed herein are apparatuses and methods for a voltage regulator with a current feedback loop. One such apparatus may include an amplifier, a master device electrically coupled to the amplifier, a slave device electrically coupled to the master device, and/or a current feedback device electrically coupled to the amplifier and the slave device to feed back current from the slave device to alter a monitoring voltage input to the amplifier.

    Apparatuses and methods for reducing read disturb
    99.
    发明授权
    Apparatuses and methods for reducing read disturb 有权
    减少读取干扰的设备和方法

    公开(公告)号：US09595339B2

    公开(公告)日：2017-03-14

    申请号：US14518727

    申请日：2014-10-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

    Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

    Abstract translation: 本文描述了用于减少读取干扰的装置和方法。 示例性装置可以包括包括第一选择栅极漏极（SGD）开关和第一选择栅极源（SGS）开关的第一存储器子块，包括第二SGD开关和第二SGS开关的第二存储器子块以及与之相关联的存取线 与第一和第二存储器子块。 该装置可以包括控制单元，其被配置为在读取操作的第一部分期间使第一和第二SGD开关以及第一和第二SGS开关能够实现，并且在第一部分期间在存取线上提供第一电压。 控制单元可以被配置为在读操作的第二部分期间禁用第一SGD开关和第一SGS开关，并且在第二部分期间在接入线上提供第二电压。

    MEMORY TIMING SELF-CALIBRATION
    100.
    发明申请
    MEMORY TIMING SELF-CALIBRATION 有权
    内存时序自校准

    公开(公告)号：US20160225420A1

    公开(公告)日：2016-08-04

    申请号：US15095347

    申请日：2016-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Ramin Ghodsi

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

    Abstract translation: 公开了用于存储器输入定时自校准的方法，用于输入定时自校准的装置和系统。 一种这样的方法包括将多个延迟微调设置顺序地编程到数据路径的延迟电路中。 数据路径可以包括耦合到延迟电路的数据锁存器。 时钟耦合到数据锁存器，将数据时钟数据插入数据锁存器。 数据的转换基本上与时钟的转换对齐。 在对每个延迟微调设置进行编程后，读取数据锁存器的输出。 在数据锁存器的第一输出状态和数据锁存器的第二输出状态之间确定边界，其中边界与多个延迟调整设置的特定延迟微调设置相关联。 特定的延迟调整设置被编程到延迟电路中。

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