中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

97 records (took 0.018 seconds)

    SILICON-ON-INSULATOR (SOI) WAFERS EMPLOYING MOLDED SUBSTRATES TO IMPROVE INSULATION AND REDUCE CURRENT LEAKAGE
    92.
    发明申请
    SILICON-ON-INSULATOR (SOI) WAFERS EMPLOYING MOLDED SUBSTRATES TO IMPROVE INSULATION AND REDUCE CURRENT LEAKAGE 审中-公开
    使用硅绝缘体（SOI）的半导体器件，用于模制基板以提高绝缘性能并降低电流泄漏

    公开(公告)号：US20160293477A1

    公开(公告)日：2016-10-06

    申请号：US14856418

    申请日：2015-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak

    IPC: H01L21/762 ,  H01L23/29 ,  H01L23/31 ,  H01L27/12 ,  H01L21/84

    CPC classification number: H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/291 ,  H01L27/1203 ,  H01L29/78603

    Abstract: Silicon-on-insulator (SOI) wafers employing molded substrates to improve insulation and reduce current leakage are provided. In one aspect, a SOI wafer comprises a substrate. An insulating layer (e.g., a buried oxide (BOX) layer) is disposed above the substrate to insulate an active semiconductor layer disposed above the insulating layer, from the substrate. Transistors are formed in the active semiconductor layer. To provide for improved insulation between the active semiconductor layer and the substrate to reduce leakage and improve performance of the active semiconductor layer, the substrate is provided in the form of a molded substrate. A coating layer is also disposed between the molded substrate and the insulating layer of the SOI wafer, in case, for example, the melting temperature of a molding compound used to form the molded substrate is not low enough to prevent contamination of the active semiconductor layer into the insulating layer.

    Abstract translation: 提供了使用模制基板以提高绝缘性并减少漏电的绝缘体上硅（SOI）晶片。 在一个方面，SOI晶片包括衬底。 绝缘层（例如，掩埋氧化物（BOX）层）设置在衬底之上，以使绝缘层上方的有源半导体层与衬底绝缘。 晶体管形成在有源半导体层中。 为了提供有源半导体层和衬底之间的改善的绝缘，以减少有源半导体层的泄漏和改善性能，衬底以模制衬底的形式提供。 在模制基板和SOI晶片的绝缘层之间也设置涂层，例如，用于形成模制基板的模塑料的熔化温度不足以防止有源半导体层的污染 进入绝缘层。

    High pass filters and low pass filters using through glass via technology
    94.
    发明授权
    High pass filters and low pass filters using through glass via technology 有权
    通过玻璃通过技术的高通滤波器和低通滤波器

    公开(公告)号：US09425761B2

    公开(公告)日：2016-08-23

    申请号：US14055707

    申请日：2013-10-16

    Applicant: QUALCOMM Incorporated

    Inventor： Chengjie Zuo ,  Jonghae Kim ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

    IPC: H03H7/01 ,  H04B1/04

    CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

    Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

    Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 贯通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

    Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods
    96.
    发明授权
    Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods 有权
    用于减少集成电路（ICS）中磁耦合的系统，以及相关组件和方法

    公开(公告)号：US09264013B2

    公开(公告)日：2016-02-16

    申请号：US14019821

    申请日：2013-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

    IPC: H03H7/46 ,  H03H3/00

    CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

    Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

    Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

    TOROID INDUCTOR IN AN INTEGRATED DEVICE
    97.
    发明申请
    TOROID INDUCTOR IN AN INTEGRATED DEVICE 有权
    集成器件中的电极电感器

    公开(公告)号：US20150115403A1

    公开(公告)日：2015-04-30

    申请号：US14063934

    申请日：2013-10-25

    Applicant: QUALCOMM Incorporated

    Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

    IPC: H01L49/02

    CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

    Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

Patent Agency Ranking