公开(公告)号：US20160124895A1

公开(公告)日：2016-05-05

申请号：US14931652

申请日：2015-11-03

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

公开(公告)号：US09106399B2

公开(公告)日：2015-08-11

申请号：US14321723

申请日：2014-07-01

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

IPC: H04L7/033 ,  H03L7/081 ,  H03L7/091 ,  H04L7/00

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract translation: 用于根据接收到的数字信号30执行时钟恢复的电路。该电路至少包括用于对数字信号进行采样的边缘采样器105和数据采样器145以及时钟信号提供电路。 时钟信号供应电路提供边缘时钟25和数据时钟20信号，其相位偏移到边缘采样器105和数据采样器145的相应时钟输入。时钟信号供应电路可操作以选择性地改变相位偏移 边沿和数据时钟信号。

公开(公告)号：US09083280B2

公开(公告)日：2015-07-14

申请号：US14452187

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Brian Leibowitz ,  Hae-Chang Lee ,  Farshid Aryanfar ,  Kun-Yung Chang ,  Jie Shen

IPC: H03D13/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/085

CPC classification number: H03D13/00 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于相位对齐的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

公开(公告)号：US08923467B2

公开(公告)日：2014-12-30

申请号：US13674812

申请日：2012-11-12

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Thomas H. Greer, III ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Mark A. Horowitz

IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/093 ,  H03L7/07

CPC classification number: H04L7/0012 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/0331 ,  H04L7/0337

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract translation: 一种用于执行时钟和数据恢复的系统和方法。 根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。

公开(公告)号：US20140333356A1

公开(公告)日：2014-11-13

申请号：US14089094

申请日：2013-11-25

Applicant: Rambus Inc.

Inventor： Farshid Aryanfar ,  Hae-Chang Lee ,  Kun-Yung Chang ,  Ting Wu ,  Carl Werner ,  Masoud Koochakzadeh

IPC: H03L7/093 ,  H03L7/08

CPC classification number: H03L7/093 ,  G06F1/10 ,  H03L7/0802

Abstract: A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

Abstract translation: 信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过 传输线。 可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。 信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。 相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。 谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。