公开(公告)号：US5646075A

公开(公告)日：1997-07-08

申请号：US559511

申请日：1995-11-15

申请人： Randhir P. S. Thakur ,  Fernando Gonzalez

发明人： Randhir P. S. Thakur ,  Fernando Gonzalez

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/324 ,  H01L21/477

CPC分类号： H01L21/31058 ,  H01L21/316 ,  H01L21/76819 ,  Y10S148/133

摘要： The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS") and has a thickness of at least 50 .ANG.. Subsequently, a barrier layer is formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer preferably comprises Si.sub.3 N.sub.4, though other suitable materials known to one of ordinary skill in the art may be employed. Further, a glass layer is then formed superjacent the barrier layer. The glass layer comprises at least one of SiO.sub.2, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass, and has a thickness of at least 1 k.ANG.. Upon forming the glass layer, the glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a substantially high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for approximately 5 seconds to 60 seconds, thereby making said glass layer substantially planar. The radiant energy generates a temperature substantially within the range of 700.degree. C. to 1250.degree. C. Further, the gas comprises at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar--H.sub.2, H.sub.2, GeH.sub.4, and a Fluorine based gas.

摘要翻译： 本发明教导了半导体制造方法。 该方法最初包括在至少两个导电层之上形成保形层的步骤。 共形层优选包括原硅酸四乙酯（“TEOS”），并且具有至少50的厚度。 随后，在保形层之上形成阻挡层，以防止随后的层扩散到活性区域。 阻挡层优选包含Si 3 N 4，尽管可以使用本领域普通技术人员已知的其它合适的材料。 此外，然后在阻挡层的上方形成玻璃层。 玻璃层包括SiO 2，磷硅酸盐玻璃，硼硅酸盐玻璃和硼磷硅酸盐玻璃中的至少一种，并且具有至少1k ANGSTROM的厚度。 在形成玻璃层时，将玻璃层加热到至少800℃的温度至少15分钟，同时在基本上高的温度下引入H 2和O 2以引起气化，从而使玻璃层回流。 接下来，玻璃层暴露于气体和辐射能量约5秒至60秒，从而使所述玻璃层基本上是平面的。 辐射能产生基本上在700℃至1250℃范围内的温度。此外，气体包括N 2，NH 3，O 2，N 2 O，Ar，Ar-H 2，H 2，GeH 4和氟中的至少一种 基气体。

公开(公告)号：US5608249A

公开(公告)日：1997-03-04

申请号：US558442

申请日：1995-11-16

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852

摘要： An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. The storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.

摘要翻译： 半导体衬底中的掺杂有源区和多晶硅上层之间的改进的存储节点结，诸如DRAM存储单元中的存储节点结。 存储节点结的面积和周长显着减小，并且结点从相邻隔离结构移开。 结合新结的示例性半导体器件包括在导电多晶硅层和半导体衬底上的有源区之间的存储节点结，衬底已经经过LOCOS步骤以产生由场氧化物区域界定的有源区。 在衬底上的有源区域上形成绝缘栅电极，其已被掺杂到第一导电类型。 包括有源区域的一部分的接触区域在栅电极的一侧和场氧化物区域之间横向延伸。 接触区域具有与栅电极相邻的第一段和介于第一段和场氧化物区之间的第二段。 因此，第一段由第二段与场氧化物区隔离。 第一段被掺杂到第二导电类型。 形成与接触区域的第一段电接触而不是接触区域的第二段的存储多晶硅层。 存储多晶硅通过介于存储多晶硅和接触区域的第二段之间的绝缘层与场氧化物隔离。

公开(公告)号：US5572461A

公开(公告)日：1996-11-05

申请号：US388873

申请日：1995-02-14

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： G11C11/402 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/402 ,  G11C11/4023 ,  Y10S257/903

摘要： The present invention is a three-transistor (3-T) SRAM cell that is made up of a half latch in combination with a dynamic random access memory (DRAM) cell. In a DRAM cell, the "0" bit state is represented by a discharged cell capacitor--a stable state. The "1" bit state, on the other hand, is represented by a charged cell capacitor--an unstable state, since the capacitor leaks rapidly toward the discharged "0" bit state. The new 3-T SRAM cell incorporates a latch which maintains the charge on the cell capacitor when the cell is in a "1" bit state. The cell circuitry includes a cell access transistor coupled to a capacitor, a pull-down transistor, and a P-channel thin film transistor (TFT) which acts as the capacitor pull-up device, the gate of the P-channel TFT also being the drain of the pull-down transistor. A separate polycrystalline silicon layer functions as the substrate of the TFT pull-up device. The 3-T SRAM cell is one half the size of a 4-T SRAM cell and about twice the size of a DRAM cell.

摘要翻译： 本发明是与动态随机存取存储器（DRAM）单元结合的半锁存器构成的三晶体管（3-T）SRAM单元。 在DRAM单元中，“0”位状态由放电单元电容器表示 - 稳定状态。 另一方面，“1”位状态由充电单元电容器 - 不稳定状态表示，因为电容器迅速向放电的“0”位状态泄漏。 新的3-T SRAM单元包含一个锁存器，当单元处于“1”位状态时，该锁存器保持单元电容器上的电荷。 单元电路包括耦合到电容器的单元存取晶体管，下拉晶体管和用作电容器上拉器件的P沟道薄膜晶体管（TFT），P沟道TFT的栅极也是 下拉晶体管的漏极。 单独的多晶硅层用作TFT上拉器件的衬底。 3-T SRAM单元是4-T SRAM单元的大小的一半，是DRAM单元大小的两倍。

公开(公告)号：US5453396A

公开(公告)日：1995-09-26

申请号：US250897

申请日：1994-05-31

申请人： Fernando Gonzalez ,  Angus C. Fox, III

发明人： Fernando Gonzalez ,  Angus C. Fox, III

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L21/76294 ,  H01L27/10808

摘要： The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apart regions on the surface of the field oxide layer; removing portions of the field oxide layer in the exposed, spaced-apart regions with an anisotropic etch so as to leave a cavity in each spaced-apart region, each cavity having as its floor an exposed region of the silicon substrate, and having vertical walls of field oxide; angularly chamfering the rim of each cavity with a facet etch; and filling each cavity with silicon using selective epitaxial growth, and using the floor of each cavity as the seed crystal for such growth.

摘要翻译： 本发明是通过以下步骤在硅衬底上形成扩散区域和场隔离区域的方法：在衬底的表面上生长场氧化物层; 形成在场氧化物层的表面上露出多个间隔开的区域的掩模图案; 通过各向异性蚀刻去除暴露的间隔开的区域中的场氧化物层的部分，以便在每个间隔开的区域中留下空腔，每个空腔具有作为其底板的硅衬底的暴露区域，并具有垂直壁 的氧化物; 用小面蚀刻对每个腔的边缘进行角度倒角; 并使用选择性外延生长用硅填充每个腔，并且使用每个腔的底部作为用于这种生长的晶种。

公开(公告)号：US5425392A

公开(公告)日：1995-06-20

申请号：US67660

申请日：1993-05-26

申请人： Randhir P. S. Thakur ,  Fernando Gonzalez ,  Annette L. Martin

发明人： Randhir P. S. Thakur ,  Fernando Gonzalez ,  Annette L. Martin

IPC分类号： H01L21/28 ,  H01L21/8239

CPC分类号： H01L21/28247 ,  H01L21/28061

摘要： The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500.degree. C. to 1250.degree. C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF.sub.6, TMAT and TiCl.sub.4.

摘要翻译： 本发明教导了一种在半导体晶片的制造中降低薄层电阻的方法。 在其中设置有其上具有栅极氧化物层的硅衬底。 随后，通过将硅衬底暴露于包括硅烷，乙硅烷和二氯硅烷中的至少一种的第一气体和基本上在500℃的温度范围内的辐射能，在栅极氧化物层的上方形成多晶硅层。 至1250℃至少10秒钟。 多晶硅衬底可以掺杂例如磷，砷和硼的材料，例如通过在所述条件下将多晶硅暴露于第二气体。 通过将多晶硅暴露于包含WF6，TMAT和TiCl4中的至少一种的第三气体，可以在多晶硅之上形成包括硅化钨（WSix）和硅化钛（TiSix）中的至少一种的导电层。

公开(公告)号：US5376566A

公开(公告)日：1994-12-27

申请号：US152116

申请日：1993-11-12

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10873 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66659 ,  H01L27/10888

摘要： An improved N-channel field-effect transistor is fabricated by performing a vertical N- implant, aligned to the vertical edges of the gate electrode, in both the source and drain regions of the device. In a first embodiment of the invention intended for use in dynamic random access memory access devices, a dielectric spacer is then formed on the sidewall of the gate electrode adjacent the drain (i.e., the regions which functions as the bitline contact in a DRAM memory cell). A vertical N+ implant, aligned to the exposed vertical edge of that spacer, is performed, in addition to an oblique implant of an N-type impurity. The oblique implant dosage is significantly greater than the N- implant dosage, but significantly less than the N+ implant dosage. In a second embodiment of the invention intended for use in applications where the transistor has no capacitive storage node, spacers are formed on both sidewalls of the gate electrode and the N+ implant, as well as the oblique N-type implant are performed in both the source and drain regions of the device. In preferred embodiments of the invention, phosphorus is utilized as the N- implant impurity, while arsenic is utilized for the other two N-type implants. The oblique implant provides not only reduced electric field strength in the channel region, but also reduced series resistance.

摘要翻译： 通过在器件的源极和漏极区域中执行与栅电极的垂直边缘对准的垂直N-注入来制造改进的N沟道场效应晶体管。 在本发明的第一实施例中，旨在用于动态随机存取存储器存取器件中，然后在邻近漏极的栅电极的侧壁上形成电介质间隔物（即，在DRAM存储器单元中用作位线接触的区域 ）。 除了N型杂质的倾斜注入之外，还执行与该间隔物的暴露的垂直边缘对准的垂直N +注入。 倾斜植入剂量显着大于N-植入剂量，但显着小于N +植入剂量。 在本发明的第二个实施例中，意图用于晶体管没有电容存储节点的应用中，在栅电极和N +注入的两个侧壁上形成间隔物，以及斜面N型注入都在 源极和漏极区域。 在本发明的优选实施方案中，磷用作N-注入杂质，而砷用于其它两种N型植入物。 倾斜植入物不仅在沟道区域中提供了降低的电场强度，而且降低了串联电阻。

公开(公告)号：US4446547A

公开(公告)日：1984-05-01

申请号：US339843

申请日：1982-01-18

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： G11B3/58

CPC分类号： G11B3/5836

摘要： A record cleaning device which attaches to the tone arm of a record player for removing dust and other undesirable material from the grooves of a phonograph record without significant interferring with the normal tracking of the phonograph cartridge. The device includes a brush for brushing the undesirable material from the grooves of the phonograph record, and an elongated strip of thin, lightweight and flexible material for flexibly supporting the brush above and in contact with the grooves of the phonograph record in which the flexing action of the brush and that of the strip in relation to the brush weight allows for joint, commensurate and comparable flexing action of both during record playback. In a further embodiment a motion damper is mounted between the brush and the strip to stop energy exchange between them and to dampen feedback vibrations to the tone arm.

摘要翻译： 记录清洁装置，其附接到记录播放器的色调臂，用于从留声机记录的凹槽除去灰尘和其它不期望的材料，而不会对留声机盒的正常跟踪造成明显的干扰。 该装置包括用于从留声机记录槽的刷毛不需要的材料的刷子，以及一薄的，重量轻且柔软的材料的细长带，用于在留声机记录的凹槽上方柔性地支撑刷子，并与其中的弯曲动作 的刷子和条带相对于刷子重量允许在记录回放期间两者的联合，相当和相当的弯曲动作。 在另一实施例中，运动阻尼器安装在刷子和带之间，以阻止它们之间的能量交换并且抑制对音调臂的反馈振动。

公开(公告)号：US08501602B2

公开(公告)日：2013-08-06

申请号：US13336516

申请日：2011-12-23

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L21/425

CPC分类号： H01L29/66636 ,  H01L21/2257 ,  H01L21/823481 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/7834

摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

摘要翻译： 用于形成诸如晶体管的器件的技术具有垂直的接合边缘。 更具体地说，在沟槽中形成浅沟槽并填充氧化物。 可以在氧化物中形成空穴并填充导电材料，例如掺杂的多晶硅。 在沟槽边缘处在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望性质的二极管延伸。

公开(公告)号：US20120208345A1

公开(公告)日：2012-08-16

申请号：US13454187

申请日：2012-04-24

申请人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

发明人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

IPC分类号： H01L21/762

CPC分类号： H01L21/76237

摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

摘要翻译： 本发明涉及在半导体衬底中形成微电子结构的方法。 该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。 绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。 间隔物可以由绝缘材料形成。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。 保形材料的平面化可能遵循。

公开(公告)号：US08173517B2

公开(公告)日：2012-05-08

申请号：US12828868

申请日：2010-07-01

申请人： Fernando Gonzalez ,  David L. Chapek ,  Randhir P. S. Thakur

发明人： Fernando Gonzalez ,  David L. Chapek ,  Randhir P. S. Thakur

IPC分类号： H01L21/764 ,  H01L29/00

CPC分类号： H01L21/76237

摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

摘要翻译： 本发明涉及在半导体衬底中形成微电子结构的方法。 该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。 绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。 间隔物可以由绝缘材料形成。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。 保形材料的平面化可能遵循。